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Text File  |  2002-07-08  |  218 b   |  12 lines
  1. // A simple 256X8 RAM
  2.  
  3. PORT address    in[0:7] ;
  4. PORT data_in    in[8:15] ;
  5. PORT data_out   out[0:7] ;
  6.  
  7. LEVEL (CLOCK=in[16], DELAY=0, WIDTH=8) RAM[256] ;
  8.  
  9. RAM[address] = data_in ;
  10.  
  11. data_out = RAM[address] ;
  12.