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C/C++ Source or Header  |  2008-12-24  |  1.1 KB  |  52 lines
  1. #ifndef __ASM_CPU_SH3_DMA_H
  2. #define __ASM_CPU_SH3_DMA_H
  3.  
  4.  
  5. #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  6.     defined(CONFIG_CPU_SUBTYPE_SH7721)
  7. #define SH_DMAC_BASE    0xa4010020
  8. #else
  9. #define SH_DMAC_BASE    0xa4000020
  10. #endif
  11.  
  12. #if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
  13. #define DMTE0_IRQ    48
  14. #define DMTE1_IRQ    49
  15. #define DMTE2_IRQ    50
  16. #define DMTE3_IRQ    51
  17. #define DMTE4_IRQ    76
  18. #define DMTE5_IRQ    77
  19. #endif
  20.  
  21. /* Definitions for the SuperH DMAC */
  22. #define TM_BURST    0x00000020
  23. #define TS_8        0x00000000
  24. #define TS_16        0x00000008
  25. #define TS_32        0x00000010
  26. #define TS_128        0x00000018
  27.  
  28. #define CHCR_TS_MASK    0x18
  29. #define CHCR_TS_SHIFT    3
  30.  
  31. #define DMAOR_INIT    DMAOR_DME
  32.  
  33. /*
  34.  * The SuperH DMAC supports a number of transmit sizes, we list them here,
  35.  * with their respective values as they appear in the CHCR registers.
  36.  */
  37. enum {
  38.     XMIT_SZ_8BIT,
  39.     XMIT_SZ_16BIT,
  40.     XMIT_SZ_32BIT,
  41.     XMIT_SZ_128BIT,
  42. };
  43.  
  44. static unsigned int ts_shift[] __maybe_unused = {
  45.     [XMIT_SZ_8BIT]        = 0,
  46.     [XMIT_SZ_16BIT]        = 1,
  47.     [XMIT_SZ_32BIT]        = 2,
  48.     [XMIT_SZ_128BIT]    = 4,
  49. };
  50.  
  51. #endif /* __ASM_CPU_SH3_DMA_H */
  52.