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C/C++ Source or Header  |  2008-12-24  |  4.0 KB  |  129 lines
  1. /*
  2.  * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
  3.  *
  4.  * Authors:     Shlomi Gridish <gridish@freescale.com>
  5.  *         Li Yang <leoli@freescale.com>
  6.  *
  7.  * Description:
  8.  * QE IC external definitions and structure.
  9.  *
  10.  * This program is free software; you can redistribute  it and/or modify it
  11.  * under  the terms of  the GNU General  Public License as published by the
  12.  * Free Software Foundation;  either version 2 of the  License, or (at your
  13.  * option) any later version.
  14.  */
  15. #ifndef _ASM_POWERPC_QE_IC_H
  16. #define _ASM_POWERPC_QE_IC_H
  17.  
  18. #include <linux/irq.h>
  19.  
  20. #define NUM_OF_QE_IC_GROUPS    6
  21.  
  22. /* Flags when we init the QE IC */
  23. #define QE_IC_SPREADMODE_GRP_W            0x00000001
  24. #define QE_IC_SPREADMODE_GRP_X            0x00000002
  25. #define QE_IC_SPREADMODE_GRP_Y            0x00000004
  26. #define QE_IC_SPREADMODE_GRP_Z            0x00000008
  27. #define QE_IC_SPREADMODE_GRP_RISCA        0x00000010
  28. #define QE_IC_SPREADMODE_GRP_RISCB        0x00000020
  29.  
  30. #define QE_IC_LOW_SIGNAL            0x00000100
  31. #define QE_IC_HIGH_SIGNAL            0x00000200
  32.  
  33. #define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH    0x00001000
  34. #define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH    0x00002000
  35. #define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH    0x00004000
  36. #define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH    0x00008000
  37. #define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH    0x00010000
  38. #define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH    0x00020000
  39. #define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH    0x00040000
  40. #define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH    0x00080000
  41. #define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH    0x00100000
  42. #define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH    0x00200000
  43. #define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH    0x00400000
  44. #define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH    0x00800000
  45. #define QE_IC_GRP_W_DEST_SIGNAL_SHIFT        (12)
  46.  
  47. /* QE interrupt sources groups */
  48. enum qe_ic_grp_id {
  49.     QE_IC_GRP_W = 0,    /* QE interrupt controller group W */
  50.     QE_IC_GRP_X,        /* QE interrupt controller group X */
  51.     QE_IC_GRP_Y,        /* QE interrupt controller group Y */
  52.     QE_IC_GRP_Z,        /* QE interrupt controller group Z */
  53.     QE_IC_GRP_RISCA,    /* QE interrupt controller RISC group A */
  54.     QE_IC_GRP_RISCB        /* QE interrupt controller RISC group B */
  55. };
  56.  
  57. void qe_ic_init(struct device_node *node, unsigned int flags,
  58.         void (*low_handler)(unsigned int irq, struct irq_desc *desc),
  59.         void (*high_handler)(unsigned int irq, struct irq_desc *desc));
  60. void qe_ic_set_highest_priority(unsigned int virq, int high);
  61. int qe_ic_set_priority(unsigned int virq, unsigned int priority);
  62. int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
  63.  
  64. struct qe_ic;
  65. unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
  66. unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
  67.  
  68. static inline void qe_ic_cascade_low_ipic(unsigned int irq,
  69.                       struct irq_desc *desc)
  70. {
  71.     struct qe_ic *qe_ic = desc->handler_data;
  72.     unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
  73.  
  74.     if (cascade_irq != NO_IRQ)
  75.         generic_handle_irq(cascade_irq);
  76. }
  77.  
  78. static inline void qe_ic_cascade_high_ipic(unsigned int irq,
  79.                        struct irq_desc *desc)
  80. {
  81.     struct qe_ic *qe_ic = desc->handler_data;
  82.     unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
  83.  
  84.     if (cascade_irq != NO_IRQ)
  85.         generic_handle_irq(cascade_irq);
  86. }
  87.  
  88. static inline void qe_ic_cascade_low_mpic(unsigned int irq,
  89.                       struct irq_desc *desc)
  90. {
  91.     struct qe_ic *qe_ic = desc->handler_data;
  92.     unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
  93.  
  94.     if (cascade_irq != NO_IRQ)
  95.         generic_handle_irq(cascade_irq);
  96.  
  97.     desc->chip->eoi(irq);
  98. }
  99.  
  100. static inline void qe_ic_cascade_high_mpic(unsigned int irq,
  101.                        struct irq_desc *desc)
  102. {
  103.     struct qe_ic *qe_ic = desc->handler_data;
  104.     unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
  105.  
  106.     if (cascade_irq != NO_IRQ)
  107.         generic_handle_irq(cascade_irq);
  108.  
  109.     desc->chip->eoi(irq);
  110. }
  111.  
  112. static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
  113.                         struct irq_desc *desc)
  114. {
  115.     struct qe_ic *qe_ic = desc->handler_data;
  116.     unsigned int cascade_irq;
  117.  
  118.     cascade_irq = qe_ic_get_high_irq(qe_ic);
  119.     if (cascade_irq == NO_IRQ)
  120.         cascade_irq = qe_ic_get_low_irq(qe_ic);
  121.  
  122.     if (cascade_irq != NO_IRQ)
  123.         generic_handle_irq(cascade_irq);
  124.  
  125.     desc->chip->eoi(irq);
  126. }
  127.  
  128. #endif /* _ASM_POWERPC_QE_IC_H */
  129.