home *** CD-ROM | disk | FTP | other *** search
/ Mac Easy 2010 May / Mac Life Ubuntu.iso / casper / filesystem.squashfs / usr / src / linux-headers-2.6.28-15 / arch / mips / include / asm / cpu.h < prev    next >
Encoding:
C/C++ Source or Header  |  2008-12-24  |  8.3 KB  |  268 lines
  1. /*
  2.  * cpu.h: Values of the PRId register used to match up
  3.  *        various MIPS cpu types.
  4.  *
  5.  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
  6.  * Copyright (C) 2004  Maciej W. Rozycki
  7.  */
  8. #ifndef _ASM_CPU_H
  9. #define _ASM_CPU_H
  10.  
  11. /* Assigned Company values for bits 23:16 of the PRId Register
  12.    (CP0 register 15, select 0).  As of the MIPS32 and MIPS64 specs from
  13.    MTI, the PRId register is defined in this (backwards compatible)
  14.    way:
  15.  
  16.   +----------------+----------------+----------------+----------------+
  17.   | Company Options| Company ID     | Processor ID   | Revision       |
  18.   +----------------+----------------+----------------+----------------+
  19.    31            24 23            16 15             8 7
  20.  
  21.    I don't have docs for all the previous processors, but my impression is
  22.    that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
  23.    spec.
  24. */
  25.  
  26. #define PRID_COMP_LEGACY    0x000000
  27. #define PRID_COMP_MIPS        0x010000
  28. #define PRID_COMP_BROADCOM    0x020000
  29. #define PRID_COMP_ALCHEMY    0x030000
  30. #define PRID_COMP_SIBYTE    0x040000
  31. #define PRID_COMP_SANDCRAFT    0x050000
  32. #define PRID_COMP_NXP       0x060000
  33. #define PRID_COMP_TOSHIBA    0x070000
  34. #define PRID_COMP_LSI        0x080000
  35. #define PRID_COMP_LEXRA        0x0b0000
  36.  
  37.  
  38. /*
  39.  * Assigned values for the product ID register.  In order to detect a
  40.  * certain CPU type exactly eventually additional registers may need to
  41.  * be examined.  These are valid when 23:16 == PRID_COMP_LEGACY
  42.  */
  43. #define PRID_IMP_R2000        0x0100
  44. #define PRID_IMP_AU1_REV1    0x0100
  45. #define PRID_IMP_AU1_REV2    0x0200
  46. #define PRID_IMP_R3000        0x0200        /* Same as R2000A  */
  47. #define PRID_IMP_R6000        0x0300        /* Same as R3000A  */
  48. #define PRID_IMP_R4000        0x0400
  49. #define PRID_IMP_R6000A        0x0600
  50. #define PRID_IMP_R10000        0x0900
  51. #define PRID_IMP_R4300        0x0b00
  52. #define PRID_IMP_VR41XX        0x0c00
  53. #define PRID_IMP_R12000        0x0e00
  54. #define PRID_IMP_R14000        0x0f00
  55. #define PRID_IMP_R8000        0x1000
  56. #define PRID_IMP_PR4450        0x1200
  57. #define PRID_IMP_R4600        0x2000
  58. #define PRID_IMP_R4700        0x2100
  59. #define PRID_IMP_TX39        0x2200
  60. #define PRID_IMP_R4640        0x2200
  61. #define PRID_IMP_R4650        0x2200        /* Same as R4640 */
  62. #define PRID_IMP_R5000        0x2300
  63. #define PRID_IMP_TX49        0x2d00
  64. #define PRID_IMP_SONIC        0x2400
  65. #define PRID_IMP_MAGIC        0x2500
  66. #define PRID_IMP_RM7000        0x2700
  67. #define PRID_IMP_NEVADA        0x2800        /* RM5260 ??? */
  68. #define PRID_IMP_RM9000        0x3400
  69. #define PRID_IMP_LOONGSON1    0x4200
  70. #define PRID_IMP_R5432        0x5400
  71. #define PRID_IMP_R5500        0x5500
  72. #define PRID_IMP_LOONGSON2    0x6300
  73.  
  74. #define PRID_IMP_UNKNOWN    0xff00
  75.  
  76. /*
  77.  * These are the PRID's for when 23:16 == PRID_COMP_MIPS
  78.  */
  79.  
  80. #define PRID_IMP_4KC        0x8000
  81. #define PRID_IMP_5KC        0x8100
  82. #define PRID_IMP_20KC        0x8200
  83. #define PRID_IMP_4KEC        0x8400
  84. #define PRID_IMP_4KSC        0x8600
  85. #define PRID_IMP_25KF        0x8800
  86. #define PRID_IMP_5KE        0x8900
  87. #define PRID_IMP_4KECR2        0x9000
  88. #define PRID_IMP_4KEMPR2    0x9100
  89. #define PRID_IMP_4KSD        0x9200
  90. #define PRID_IMP_24K        0x9300
  91. #define PRID_IMP_34K        0x9500
  92. #define PRID_IMP_24KE        0x9600
  93. #define PRID_IMP_74K        0x9700
  94. #define PRID_IMP_1004K        0x9900
  95.  
  96. /*
  97.  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
  98.  */
  99.  
  100. #define PRID_IMP_SB1            0x0100
  101. #define PRID_IMP_SB1A           0x1100
  102.  
  103. /*
  104.  * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
  105.  */
  106.  
  107. #define PRID_IMP_SR71000        0x0400
  108.  
  109. /*
  110.  * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
  111.  */
  112.  
  113. #define PRID_IMP_BCM4710    0x4000
  114. #define PRID_IMP_BCM3302    0x9000
  115.  
  116. /*
  117.  * Definitions for 7:0 on legacy processors
  118.  */
  119.  
  120. #define PRID_REV_MASK        0x00ff
  121.  
  122. #define PRID_REV_TX4927        0x0022
  123. #define PRID_REV_TX4937        0x0030
  124. #define PRID_REV_R4400        0x0040
  125. #define PRID_REV_R3000A        0x0030
  126. #define PRID_REV_R3000        0x0020
  127. #define PRID_REV_R2000A        0x0010
  128. #define PRID_REV_TX3912     0x0010
  129. #define PRID_REV_TX3922     0x0030
  130. #define PRID_REV_TX3927     0x0040
  131. #define PRID_REV_VR4111        0x0050
  132. #define PRID_REV_VR4181        0x0050    /* Same as VR4111 */
  133. #define PRID_REV_VR4121        0x0060
  134. #define PRID_REV_VR4122        0x0070
  135. #define PRID_REV_VR4181A    0x0070    /* Same as VR4122 */
  136. #define PRID_REV_VR4130        0x0080
  137. #define PRID_REV_34K_V1_0_2    0x0022
  138.  
  139. /*
  140.  * Older processors used to encode processor version and revision in two
  141.  * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
  142.  * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
  143.  * the patch number.  *ARGH*
  144.  */
  145. #define PRID_REV_ENCODE_44(ver, rev)                    \
  146.     ((ver) << 4 | (rev))
  147. #define PRID_REV_ENCODE_332(ver, rev, patch)                \
  148.     ((ver) << 5 | (rev) << 2 | (patch))
  149.  
  150. /*
  151.  * FPU implementation/revision register (CP1 control register 0).
  152.  *
  153.  * +---------------------------------+----------------+----------------+
  154.  * | 0                               | Implementation | Revision       |
  155.  * +---------------------------------+----------------+----------------+
  156.  *  31                             16 15             8 7              0
  157.  */
  158.  
  159. #define FPIR_IMP_NONE        0x0000
  160.  
  161. enum cpu_type_enum {
  162.     CPU_UNKNOWN,
  163.  
  164.     /*
  165.      * R2000 class processors
  166.      */
  167.     CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
  168.     CPU_R3081, CPU_R3081E,
  169.  
  170.     /*
  171.      * R6000 class processors
  172.      */
  173.     CPU_R6000, CPU_R6000A,
  174.  
  175.     /*
  176.      * R4000 class processors
  177.      */
  178.     CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
  179.     CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
  180.     CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432,
  181.     CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
  182.     CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
  183.     CPU_SR71000, CPU_RM9000, CPU_TX49XX,
  184.  
  185.     /*
  186.      * R8000 class processors
  187.      */
  188.     CPU_R8000,
  189.  
  190.     /*
  191.      * TX3900 class processors
  192.      */
  193.     CPU_TX3912, CPU_TX3922, CPU_TX3927,
  194.  
  195.     /*
  196.      * MIPS32 class processors
  197.      */
  198.     CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
  199.     CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500,
  200.     CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
  201.  
  202.     /*
  203.      * MIPS64 class processors
  204.      */
  205.     CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
  206.  
  207.     CPU_LAST
  208. };
  209.  
  210.  
  211. /*
  212.  * ISA Level encodings
  213.  *
  214.  */
  215. #define MIPS_CPU_ISA_I        0x00000001
  216. #define MIPS_CPU_ISA_II        0x00000002
  217. #define MIPS_CPU_ISA_III    0x00000004
  218. #define MIPS_CPU_ISA_IV        0x00000008
  219. #define MIPS_CPU_ISA_V        0x00000010
  220. #define MIPS_CPU_ISA_M32R1    0x00000020
  221. #define MIPS_CPU_ISA_M32R2    0x00000040
  222. #define MIPS_CPU_ISA_M64R1    0x00000080
  223. #define MIPS_CPU_ISA_M64R2    0x00000100
  224.  
  225. #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
  226.     MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
  227. #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
  228.     MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
  229.  
  230. /*
  231.  * CPU Option encodings
  232.  */
  233. #define MIPS_CPU_TLB        0x00000001 /* CPU has TLB */
  234. #define MIPS_CPU_4KEX        0x00000002 /* "R4K" exception model */
  235. #define MIPS_CPU_3K_CACHE    0x00000004 /* R3000-style caches */
  236. #define MIPS_CPU_4K_CACHE    0x00000008 /* R4000-style caches */
  237. #define MIPS_CPU_TX39_CACHE    0x00000010 /* TX3900-style caches */
  238. #define MIPS_CPU_FPU        0x00000020 /* CPU has FPU */
  239. #define MIPS_CPU_32FPR        0x00000040 /* 32 dbl. prec. FP registers */
  240. #define MIPS_CPU_COUNTER    0x00000080 /* Cycle count/compare */
  241. #define MIPS_CPU_WATCH        0x00000100 /* watchpoint registers */
  242. #define MIPS_CPU_DIVEC        0x00000200 /* dedicated interrupt vector */
  243. #define MIPS_CPU_VCE        0x00000400 /* virt. coherence conflict possible */
  244. #define MIPS_CPU_CACHE_CDEX_P    0x00000800 /* Create_Dirty_Exclusive CACHE op */
  245. #define MIPS_CPU_CACHE_CDEX_S    0x00001000 /* ... same for seconary cache ... */
  246. #define MIPS_CPU_MCHECK        0x00002000 /* Machine check exception */
  247. #define MIPS_CPU_EJTAG        0x00004000 /* EJTAG exception */
  248. #define MIPS_CPU_NOFPUEX    0x00008000 /* no FPU exception */
  249. #define MIPS_CPU_LLSC        0x00010000 /* CPU has ll/sc instructions */
  250. #define MIPS_CPU_INCLUSIVE_CACHES    0x00020000 /* P-cache subset enforced */
  251. #define MIPS_CPU_PREFETCH    0x00040000 /* CPU has usable prefetch */
  252. #define MIPS_CPU_VINT        0x00080000 /* CPU supports MIPSR2 vectored interrupts */
  253. #define MIPS_CPU_VEIC        0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
  254. #define MIPS_CPU_ULRI        0x00200000 /* CPU has ULRI feature */
  255.  
  256. /*
  257.  * CPU ASE encodings
  258.  */
  259. #define MIPS_ASE_MIPS16        0x00000001 /* code compression */
  260. #define MIPS_ASE_MDMX        0x00000002 /* MIPS digital media extension */
  261. #define MIPS_ASE_MIPS3D        0x00000004 /* MIPS-3D */
  262. #define MIPS_ASE_SMARTMIPS    0x00000008 /* SmartMIPS */
  263. #define MIPS_ASE_DSP        0x00000010 /* Signal Processing ASE */
  264. #define MIPS_ASE_MIPSMT        0x00000020 /* CPU supports MIPS MT */
  265.  
  266.  
  267. #endif /* _ASM_CPU_H */
  268.