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Text File  |  1989-03-01  |  3.6 KB  |  62 lines
  1. Release Notes for CUPL - Universal Compiler for Programmable Logic
  2. Copyright (C) 1983, 1989 Logical Devices, Inc.
  3.  
  4.  
  5. CUPL        Release
  6. Version     Date        NOTES
  7. ----------------------------------------------------------------------------
  8.  
  9. 3.00         2/27/89    Fixed  problem  with  single   p-terms  losing  their
  10.                         polarity.  CSIM will  now correctly  simulate a clock
  11.                         mux and asynchronous clocked devices.  CSIM also  has
  12.                         the ability to display simulation output in waveform.
  13.                         An optional  front-end menu  has been added  to allow
  14.                         for easier use of CUPL.  A macro capability  has been
  15.                         added to  simplify  common logic  constructs (adders,
  16.                         decoders, counters, etc.).   A REPEAT  command allows
  17.                         indexing of equations,  which reduces  many redundant
  18.                         statements to a simple indexed loop.
  19.  
  20.                         Added support for:    Altera       EP1800/1810
  21.                                               AMD          PAL 14R21
  22.                                               AMD          PAL 22IP6
  23.                                               AMD          PAL 26V12
  24.                                               Atmel        ATV2500
  25.                                               Cypress      PLD 7C330
  26.                                               Cypress      PLD 7C331
  27.                                               Cypress      PLD 7C332
  28.                                               Gazelle      GA23SV8
  29.                                               ICT          PEEL253
  30.                                               ICT          PEEL273
  31.                                               ICT          PEEL20CG10
  32.                                               ICT          PEEL22CV10Z
  33.                                               Intel        5C180
  34.                                               MMI          PALC18U8
  35.                                               National     PAL1016P4
  36.                                               National     PAL1016LM4
  37.                                               National     PAL1016RM4
  38.                                               TI           TIBPAD18N8
  39.                                               TI           TICPAL18V8
  40.                                               TI           TIFPLA839lcc
  41.  
  42.  
  43.                         Device changes:
  44.                         ---------------
  45.                         f157     rev 15   Corrected OE simulation problem
  46.                                           for pin 6
  47.                         g6001    rev 10   Corrected architecture fuse
  48.                                           configuration
  49.                         p1016ld4 rev 02   Corrected output polarity
  50.                         p1016ld8 rev 02   Corrected output polarity
  51.                         p1016rd4 rev 02   Corrected output polarity
  52.                         p1016rd8 rev 02   Corrected output polarity
  53.                         p29ma16  rev 07   Corrected total number of fuses
  54.                         plx448   rev 11   Corrected architecture fuse
  55.                                           configuration.
  56.                         v750     rev 03   Corrected registered feedback
  57.                                           polarity and pin 18 I/O column
  58.                                           numbering problem
  59.  
  60.                         GAL devices:      Changed order of UES bit field to
  61.                                           comply with proposed JEDEC standard
  62.