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  1.  
  2. Release Notes for CUPL - Universal Compiler for Programmable Logic
  3.  
  4. CUPL        Release
  5. Version     Date        NOTES
  6. -----------------------------------------------------------------------
  7. 1.01a        9/10/83    First production release of CUPL with universal
  8.                         design support for 29 devices.
  9.  
  10. 1.01b       10/31/83    Fixes for various devices including M16C1 and
  11.                         N16C1.  Fix in CSIM to simulate 16 product
  12.                         terms in PAL16C1.  Distribute on double-sided
  13.                         diskettes (MS/PC-DOS).
  14.  
  15. 2.00a       11/19/84    First release of newly structured CUPL, using
  16.                         device database with support for 76 devices.
  17.                         Added support for PAL XOR devices, IFL JK and RS
  18.                         devices.  Improved simulator handling of
  19.                         asynchronous feedback.  Many new syntax features
  20.                         including outputs grouped as fields, numbers,
  21.                         and function table input.  Added full logic
  22.                         minimization.
  23.  
  24. 2.01a       12/21/84    Restructuring of distribution diskettes for
  25.                         proper installation (MS/PC-DOS).  CSIM properly
  26.                         removes existing vectors in JEDEC file before
  27.                         appending new test vectors.  CSIM properly renames
  28.                         JEDEC file when $exit directive used.  CSIM
  29.                         properly simulates programmable polarity before
  30.                         the output register.
  31.  
  32.                         Added support for:    AMD  AmPAL18P8
  33.                                               MMI  PAL6L16
  34.                                               MMI  PAL8L14
  35.                         Device changes:
  36.                         ---------------
  37.                         p16rp4   rev 11   Fix for simulation of
  38.                         p16rp6   rev 11      programmable polarity before
  39.                         p16rp8   rev 11      output register.
  40.                         p32r16   rev 06   MMI changed JEDEC fuse spec.
  41.                         p64r32   rev 06   MMI changed JEDEC fuse spec.
  42.                         f103     rev 07   Fixed polarity of output pins.
  43.                         f155     rev 08   Fixed HL plot for register
  44.                         f157     rev 07      RESET/PRESET & Complement
  45.                         f159     rev 12      array.  Fixed polarity of
  46.                                              non-registered output pins.
  47.                         f162     rev 04   Fixed polarity of output pins.
  48.                         f163     rev 04   Fixed polarity of output pins.
  49.                         p20rs4   rev 16   Fix for simulation of
  50.                         p20rs8   rev 14      programmable polarity before
  51.                         p20rs10  rev 15      output register.
  52.  
  53. 2.02a        1/17/85    Incorporates faster, more memory efficient
  54.                         algorithm for DeMorgan property.
  55.  
  56.                         Added support for:    MMI  PAL20RA10
  57.                                               MMI  PAL20P8E
  58.                         Device changes:
  59.                         ---------------
  60.                         p16rp4   rev 11   Fix for simulation of
  61.                         p16rp6   rev 11      programmable polarity before
  62.  
  63. 2.02b        3/20/85    Fixes for various devices.  Clarify certain error
  64.                         messages.  Made -g flag work.  Added out of memory
  65.                         error message for logic minimizer.  Improved CSIM
  66.                         error reporting.
  67.  
  68.                         Device changes:
  69.                         ---------------
  70.                         ep300   rev 15    Added warnings for SP/AR terms.
  71.                                              Fixed polarity for pin 1.
  72.                         p20ra10 rev 08    Fixed simulation error on pin 20.
  73.                         p20rs4  rev 17    Fixed number of fuses in JEDEC.
  74.                         p20s10  rev 14    Fixed number of fuses in JEDEC.
  75.                         p32r16  rev 09    No functional change.
  76.                         p64r32  rev 12    Allow pin 44 to be input.
  77.                                              Allow combinatorial output mode.
  78.                         f155    rev 10    Fixed HL plot for complement
  79.                         f157    rev 09       array.
  80.                         f159    rev 15    Fixed HL plot for complement
  81.                                              array and output enable terms.
  82.                                              Fixed default for pin 6 to be
  83.                                              active when used as an output.
  84.                         f105    rev 15    Fixed HL plot for complement
  85.                         f167    rev 15       array.  Allow AP extension
  86.                                              on internal node flip-flops.
  87.  
  88. 2.02c        5/30/85    Fixed ASCII-HEX generation for PROMs.
  89.  
  90.                         Device changes:
  91.                         ---------------
  92.                         p20p8e   rev 02   Fixed polarity for output pins.
  93.  
  94. 2.10a        3/11/86    Added state machine syntax for all registered
  95.                         devices.  Added user defined functions and new truth
  96.                         table format.  Improved logic minimization and
  97.                         DeMorgan algorithms.  Time/date stamp on all output
  98.                         files.  Print chip diagram in documentation file.
  99.                         Fixed fuse plot generation for FPLA (Signetics)
  100.                         devices when product terms merged.  Use up to 640K 
  101.                         on MS/PC-DOS version.
  102.  
  103.                         Added support for:    Altera     EP600 (limited)
  104.                                               Lattice    GAL16V8, GAL20V8
  105.                                               MMI        PAL16RA8
  106.                                               National   PL1016P8, PL10016P8
  107.                                               National   PL1016RP8, PL10016RP8
  108.                                               Panatech   EPL10P8, EPL12P6
  109.                                                  Ricoh   EPL14P2, EPL16P8
  110.                                                  VTI     EPL16RP4, RP6, RP8
  111.                                               Signetics  82S151, 82S168
  112.                                               Signetics  82S173, 82S179
  113.                                               T.I.       PLR19L8, PLR19R4
  114.                                               T.I.       PLR19R6, PLR19R8
  115.                                               T.I.       FPGA529
  116.  
  117.                         Device changes:
  118.                         ---------------
  119.                         f157     rev 13   Fixed HL plot for bank A reset and
  120.                                              preset terms.
  121.                         f162     rev 07   Signetics changed JEDEC fuse spec.
  122.                         f163     rev 07   Signetics changed JEDEC fuse spec.
  123.                         p14p4    rev 07   Fixed error in fuse map.
  124.                         p20rs10  rev 19   Fixed output enable for pin 14.
  125.                         p1020p8  rev 06   Created from p20p8e when MMI
  126.                                              changed pinout.
  127.