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C/C++ Source or Header  |  2006-08-11  |  29.9 KB  |  761 lines
  1. /*
  2.  * This file is subject to the terms and conditions of the GNU General Public
  3.  * License.  See the file "COPYING" in the main directory of this archive
  4.  * for more details.
  5.  *
  6.  * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
  7.  */
  8.  
  9. #ifndef __ASM_IA64_SN_TIOCE_H__
  10. #define __ASM_IA64_SN_TIOCE_H__
  11.  
  12. /* CE ASIC part & mfgr information  */
  13. #define TIOCE_PART_NUM            0xCE00
  14. #define TIOCE_SRC_ID            0x01
  15. #define TIOCE_REV_A            0x1
  16.  
  17. /* CE Virtual PPB Vendor/Device IDs */
  18. #define CE_VIRT_PPB_VENDOR_ID        0x10a9
  19. #define CE_VIRT_PPB_DEVICE_ID        0x4002
  20.  
  21. /* CE Host Bridge Vendor/Device IDs */
  22. #define CE_HOST_BRIDGE_VENDOR_ID    0x10a9
  23. #define CE_HOST_BRIDGE_DEVICE_ID    0x4001
  24.  
  25.  
  26. #define TIOCE_NUM_M40_ATES        4096
  27. #define TIOCE_NUM_M3240_ATES        2048
  28. #define TIOCE_NUM_PORTS            2
  29.  
  30. /*
  31.  * Register layout for TIOCE.  MMR offsets are shown at the far right of the
  32.  * structure definition.
  33.  */
  34. typedef volatile struct tioce {
  35.     /*
  36.      * ADMIN : Administration Registers
  37.      */
  38.     u64    ce_adm_id;                /* 0x000000 */
  39.     u64    ce_pad_000008;                /* 0x000008 */
  40.     u64    ce_adm_dyn_credit_status;        /* 0x000010 */
  41.     u64    ce_adm_last_credit_status;        /* 0x000018 */
  42.     u64    ce_adm_credit_limit;            /* 0x000020 */
  43.     u64    ce_adm_force_credit;            /* 0x000028 */
  44.     u64    ce_adm_control;                /* 0x000030 */
  45.     u64    ce_adm_mmr_chn_timeout;            /* 0x000038 */
  46.     u64    ce_adm_ssp_ure_timeout;            /* 0x000040 */
  47.     u64    ce_adm_ssp_dre_timeout;            /* 0x000048 */
  48.     u64    ce_adm_ssp_debug_sel;            /* 0x000050 */
  49.     u64    ce_adm_int_status;            /* 0x000058 */
  50.     u64    ce_adm_int_status_alias;        /* 0x000060 */
  51.     u64    ce_adm_int_mask;            /* 0x000068 */
  52.     u64    ce_adm_int_pending;            /* 0x000070 */
  53.     u64    ce_adm_force_int;            /* 0x000078 */
  54.     u64    ce_adm_ure_ups_buf_barrier_flush;    /* 0x000080 */
  55.     u64    ce_adm_int_dest[15];        /* 0x000088 -- 0x0000F8 */
  56.     u64    ce_adm_error_summary;            /* 0x000100 */
  57.     u64    ce_adm_error_summary_alias;        /* 0x000108 */
  58.     u64    ce_adm_error_mask;            /* 0x000110 */
  59.     u64    ce_adm_first_error;            /* 0x000118 */
  60.     u64    ce_adm_error_overflow;            /* 0x000120 */
  61.     u64    ce_adm_error_overflow_alias;        /* 0x000128 */
  62.     u64    ce_pad_000130[2];        /* 0x000130 -- 0x000138 */
  63.     u64    ce_adm_tnum_error;            /* 0x000140 */
  64.     u64    ce_adm_mmr_err_detail;            /* 0x000148 */
  65.     u64    ce_adm_msg_sram_perr_detail;        /* 0x000150 */
  66.     u64    ce_adm_bap_sram_perr_detail;        /* 0x000158 */
  67.     u64    ce_adm_ce_sram_perr_detail;        /* 0x000160 */
  68.     u64    ce_adm_ce_credit_oflow_detail;        /* 0x000168 */
  69.     u64    ce_adm_tx_link_idle_max_timer;        /* 0x000170 */
  70.     u64    ce_adm_pcie_debug_sel;            /* 0x000178 */
  71.     u64    ce_pad_000180[16];        /* 0x000180 -- 0x0001F8 */
  72.  
  73.     u64    ce_adm_pcie_debug_sel_top;        /* 0x000200 */
  74.     u64    ce_adm_pcie_debug_lat_sel_lo_top;    /* 0x000208 */
  75.     u64    ce_adm_pcie_debug_lat_sel_hi_top;    /* 0x000210 */
  76.     u64    ce_adm_pcie_debug_trig_sel_top;        /* 0x000218 */
  77.     u64    ce_adm_pcie_debug_trig_lat_sel_lo_top;    /* 0x000220 */
  78.     u64    ce_adm_pcie_debug_trig_lat_sel_hi_top;    /* 0x000228 */
  79.     u64    ce_adm_pcie_trig_compare_top;        /* 0x000230 */
  80.     u64    ce_adm_pcie_trig_compare_en_top;    /* 0x000238 */
  81.     u64    ce_adm_ssp_debug_sel_top;        /* 0x000240 */
  82.     u64    ce_adm_ssp_debug_lat_sel_lo_top;    /* 0x000248 */
  83.     u64    ce_adm_ssp_debug_lat_sel_hi_top;    /* 0x000250 */
  84.     u64    ce_adm_ssp_debug_trig_sel_top;        /* 0x000258 */
  85.     u64    ce_adm_ssp_debug_trig_lat_sel_lo_top;    /* 0x000260 */
  86.     u64    ce_adm_ssp_debug_trig_lat_sel_hi_top;    /* 0x000268 */
  87.     u64    ce_adm_ssp_trig_compare_top;        /* 0x000270 */
  88.     u64    ce_adm_ssp_trig_compare_en_top;        /* 0x000278 */
  89.     u64    ce_pad_000280[48];        /* 0x000280 -- 0x0003F8 */
  90.  
  91.     u64    ce_adm_bap_ctrl;            /* 0x000400 */
  92.     u64    ce_pad_000408[127];        /* 0x000408 -- 0x0007F8 */
  93.  
  94.     u64    ce_msg_buf_data63_0[35];    /* 0x000800 -- 0x000918 */
  95.     u64    ce_pad_000920[29];        /* 0x000920 -- 0x0009F8 */
  96.  
  97.     u64    ce_msg_buf_data127_64[35];  /* 0x000A00 -- 0x000B18 */
  98.     u64    ce_pad_000B20[29];        /* 0x000B20 -- 0x000BF8 */
  99.  
  100.     u64    ce_msg_buf_parity[35];        /* 0x000C00 -- 0x000D18 */
  101.     u64    ce_pad_000D20[29];        /* 0x000D20 -- 0x000DF8 */
  102.  
  103.     u64    ce_pad_000E00[576];        /* 0x000E00 -- 0x001FF8 */
  104.  
  105.     /*
  106.      * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
  107.      * Link#1 MMRs at start at 0x002000, Link#2 MMRs at 0x003000
  108.      * NOTE: the comment offsets at far right: let 'z' = {2 or 3}
  109.      */
  110.     #define ce_lsi(link_num)    ce_lsi[link_num-1]
  111.     struct ce_lsi_reg {
  112.         u64    ce_lsi_lpu_id;            /* 0x00z000 */
  113.         u64    ce_lsi_rst;            /* 0x00z008 */
  114.         u64    ce_lsi_dbg_stat;        /* 0x00z010 */
  115.         u64    ce_lsi_dbg_cfg;            /* 0x00z018 */
  116.         u64    ce_lsi_ltssm_ctrl;        /* 0x00z020 */
  117.         u64    ce_lsi_lk_stat;            /* 0x00z028 */
  118.         u64    ce_pad_00z030[2];   /* 0x00z030 -- 0x00z038 */
  119.         u64    ce_lsi_int_and_stat;        /* 0x00z040 */
  120.         u64    ce_lsi_int_mask;        /* 0x00z048 */
  121.         u64    ce_pad_00z050[22];  /* 0x00z050 -- 0x00z0F8 */
  122.         u64    ce_lsi_lk_perf_cnt_sel;        /* 0x00z100 */
  123.         u64    ce_pad_00z108;            /* 0x00z108 */
  124.         u64    ce_lsi_lk_perf_cnt_ctrl;    /* 0x00z110 */
  125.         u64    ce_pad_00z118;            /* 0x00z118 */
  126.         u64    ce_lsi_lk_perf_cnt1;        /* 0x00z120 */
  127.         u64    ce_lsi_lk_perf_cnt1_test;    /* 0x00z128 */
  128.         u64    ce_lsi_lk_perf_cnt2;        /* 0x00z130 */
  129.         u64    ce_lsi_lk_perf_cnt2_test;    /* 0x00z138 */
  130.         u64    ce_pad_00z140[24];  /* 0x00z140 -- 0x00z1F8 */
  131.         u64    ce_lsi_lk_lyr_cfg;        /* 0x00z200 */
  132.         u64    ce_lsi_lk_lyr_status;        /* 0x00z208 */
  133.         u64    ce_lsi_lk_lyr_int_stat;        /* 0x00z210 */
  134.         u64    ce_lsi_lk_ly_int_stat_test;    /* 0x00z218 */
  135.         u64    ce_lsi_lk_ly_int_stat_mask;    /* 0x00z220 */
  136.         u64    ce_pad_00z228[3];   /* 0x00z228 -- 0x00z238 */
  137.         u64    ce_lsi_fc_upd_ctl;        /* 0x00z240 */
  138.         u64    ce_pad_00z248[3];   /* 0x00z248 -- 0x00z258 */
  139.         u64    ce_lsi_flw_ctl_upd_to_timer;    /* 0x00z260 */
  140.         u64    ce_lsi_flw_ctl_upd_timer0;    /* 0x00z268 */
  141.         u64    ce_lsi_flw_ctl_upd_timer1;    /* 0x00z270 */
  142.         u64    ce_pad_00z278[49];  /* 0x00z278 -- 0x00z3F8 */
  143.         u64    ce_lsi_freq_nak_lat_thrsh;    /* 0x00z400 */
  144.         u64    ce_lsi_ack_nak_lat_tmr;        /* 0x00z408 */
  145.         u64    ce_lsi_rply_tmr_thr;        /* 0x00z410 */
  146.         u64    ce_lsi_rply_tmr;        /* 0x00z418 */
  147.         u64    ce_lsi_rply_num_stat;        /* 0x00z420 */
  148.         u64    ce_lsi_rty_buf_max_addr;    /* 0x00z428 */
  149.         u64    ce_lsi_rty_fifo_ptr;        /* 0x00z430 */
  150.         u64    ce_lsi_rty_fifo_rd_wr_ptr;    /* 0x00z438 */
  151.         u64    ce_lsi_rty_fifo_cred;        /* 0x00z440 */
  152.         u64    ce_lsi_seq_cnt;            /* 0x00z448 */
  153.         u64    ce_lsi_ack_sent_seq_num;    /* 0x00z450 */
  154.         u64    ce_lsi_seq_cnt_fifo_max_addr;    /* 0x00z458 */
  155.         u64    ce_lsi_seq_cnt_fifo_ptr;    /* 0x00z460 */
  156.         u64    ce_lsi_seq_cnt_rd_wr_ptr;    /* 0x00z468 */
  157.         u64    ce_lsi_tx_lk_ts_ctl;        /* 0x00z470 */
  158.         u64    ce_pad_00z478;            /* 0x00z478 */
  159.         u64    ce_lsi_mem_addr_ctl;        /* 0x00z480 */
  160.         u64    ce_lsi_mem_d_ld0;        /* 0x00z488 */
  161.         u64    ce_lsi_mem_d_ld1;        /* 0x00z490 */
  162.         u64    ce_lsi_mem_d_ld2;        /* 0x00z498 */
  163.         u64    ce_lsi_mem_d_ld3;        /* 0x00z4A0 */
  164.         u64    ce_lsi_mem_d_ld4;        /* 0x00z4A8 */
  165.         u64    ce_pad_00z4B0[2];   /* 0x00z4B0 -- 0x00z4B8 */
  166.         u64    ce_lsi_rty_d_cnt;        /* 0x00z4C0 */
  167.         u64    ce_lsi_seq_buf_cnt;        /* 0x00z4C8 */
  168.         u64    ce_lsi_seq_buf_bt_d;        /* 0x00z4D0 */
  169.         u64    ce_pad_00z4D8;            /* 0x00z4D8 */
  170.         u64    ce_lsi_ack_lat_thr;        /* 0x00z4E0 */
  171.         u64    ce_pad_00z4E8[3];   /* 0x00z4E8 -- 0x00z4F8 */
  172.         u64    ce_lsi_nxt_rcv_seq_1_cntr;    /* 0x00z500 */
  173.         u64    ce_lsi_unsp_dllp_rcvd;        /* 0x00z508 */
  174.         u64    ce_lsi_rcv_lk_ts_ctl;        /* 0x00z510 */
  175.         u64    ce_pad_00z518[29];  /* 0x00z518 -- 0x00z5F8 */
  176.         u64    ce_lsi_phy_lyr_cfg;        /* 0x00z600 */
  177.         u64    ce_pad_00z608;            /* 0x00z608 */
  178.         u64    ce_lsi_phy_lyr_int_stat;    /* 0x00z610 */
  179.         u64    ce_lsi_phy_lyr_int_stat_test;    /* 0x00z618 */
  180.         u64    ce_lsi_phy_lyr_int_mask;    /* 0x00z620 */
  181.         u64    ce_pad_00z628[11];  /* 0x00z628 -- 0x00z678 */
  182.         u64    ce_lsi_rcv_phy_cfg;        /* 0x00z680 */
  183.         u64    ce_lsi_rcv_phy_stat1;        /* 0x00z688 */
  184.         u64    ce_lsi_rcv_phy_stat2;        /* 0x00z690 */
  185.         u64    ce_lsi_rcv_phy_stat3;        /* 0x00z698 */
  186.         u64    ce_lsi_rcv_phy_int_stat;    /* 0x00z6A0 */
  187.         u64    ce_lsi_rcv_phy_int_stat_test;    /* 0x00z6A8 */
  188.         u64    ce_lsi_rcv_phy_int_mask;    /* 0x00z6B0 */
  189.         u64    ce_pad_00z6B8[9];   /* 0x00z6B8 -- 0x00z6F8 */
  190.         u64    ce_lsi_tx_phy_cfg;        /* 0x00z700 */
  191.         u64    ce_lsi_tx_phy_stat;        /* 0x00z708 */
  192.         u64    ce_lsi_tx_phy_int_stat;        /* 0x00z710 */
  193.         u64    ce_lsi_tx_phy_int_stat_test;    /* 0x00z718 */
  194.         u64    ce_lsi_tx_phy_int_mask;        /* 0x00z720 */
  195.         u64    ce_lsi_tx_phy_stat2;        /* 0x00z728 */
  196.         u64    ce_pad_00z730[10];  /* 0x00z730 -- 0x00z77F */
  197.         u64    ce_lsi_ltssm_cfg1;        /* 0x00z780 */
  198.         u64    ce_lsi_ltssm_cfg2;        /* 0x00z788 */
  199.         u64    ce_lsi_ltssm_cfg3;        /* 0x00z790 */
  200.         u64    ce_lsi_ltssm_cfg4;        /* 0x00z798 */
  201.         u64    ce_lsi_ltssm_cfg5;        /* 0x00z7A0 */
  202.         u64    ce_lsi_ltssm_stat1;        /* 0x00z7A8 */
  203.         u64    ce_lsi_ltssm_stat2;        /* 0x00z7B0 */
  204.         u64    ce_lsi_ltssm_int_stat;        /* 0x00z7B8 */
  205.         u64    ce_lsi_ltssm_int_stat_test;    /* 0x00z7C0 */
  206.         u64    ce_lsi_ltssm_int_mask;        /* 0x00z7C8 */
  207.         u64    ce_lsi_ltssm_stat_wr_en;    /* 0x00z7D0 */
  208.         u64    ce_pad_00z7D8[5];   /* 0x00z7D8 -- 0x00z7F8 */
  209.         u64    ce_lsi_gb_cfg1;            /* 0x00z800 */
  210.         u64    ce_lsi_gb_cfg2;            /* 0x00z808 */
  211.         u64    ce_lsi_gb_cfg3;            /* 0x00z810 */
  212.         u64    ce_lsi_gb_cfg4;            /* 0x00z818 */
  213.         u64    ce_lsi_gb_stat;            /* 0x00z820 */
  214.         u64    ce_lsi_gb_int_stat;        /* 0x00z828 */
  215.         u64    ce_lsi_gb_int_stat_test;    /* 0x00z830 */
  216.         u64    ce_lsi_gb_int_mask;        /* 0x00z838 */
  217.         u64    ce_lsi_gb_pwr_dn1;        /* 0x00z840 */
  218.         u64    ce_lsi_gb_pwr_dn2;        /* 0x00z848 */
  219.         u64    ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
  220.     } ce_lsi[2];
  221.  
  222.     u64    ce_pad_004000[10];        /* 0x004000 -- 0x004048 */
  223.  
  224.     /*
  225.      * CRM: Coretalk Receive Module Registers
  226.      */
  227.     u64    ce_crm_debug_mux;            /* 0x004050 */
  228.     u64    ce_pad_004058;                /* 0x004058 */
  229.     u64    ce_crm_ssp_err_cmd_wrd;            /* 0x004060 */
  230.     u64    ce_crm_ssp_err_addr;            /* 0x004068 */
  231.     u64    ce_crm_ssp_err_syn;            /* 0x004070 */
  232.  
  233.     u64    ce_pad_004078[499];        /* 0x004078 -- 0x005008 */
  234.  
  235.     /*
  236.          * CXM: Coretalk Xmit Module Registers
  237.          */
  238.     u64    ce_cxm_dyn_credit_status;        /* 0x005010 */
  239.     u64    ce_cxm_last_credit_status;        /* 0x005018 */
  240.     u64    ce_cxm_credit_limit;            /* 0x005020 */
  241.     u64    ce_cxm_force_credit;            /* 0x005028 */
  242.     u64    ce_cxm_disable_bypass;            /* 0x005030 */
  243.     u64    ce_pad_005038[3];        /* 0x005038 -- 0x005048 */
  244.     u64    ce_cxm_debug_mux;            /* 0x005050 */
  245.  
  246.         u64        ce_pad_005058[501];         /* 0x005058 -- 0x005FF8 */
  247.  
  248.     /*
  249.      * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
  250.      * DTL: Link#1 MMRs at start at 0x006000, Link#2 MMRs at 0x008000
  251.      * DTL: the comment offsets at far right: let 'y' = {6 or 8}
  252.      *
  253.      * UTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
  254.      * UTL: Link#1 MMRs at start at 0x007000, Link#2 MMRs at 0x009000
  255.      * UTL: the comment offsets at far right: let 'z' = {7 or 9}
  256.      */
  257.     #define ce_dtl(link_num)    ce_dtl_utl[link_num-1]
  258.     #define ce_utl(link_num)    ce_dtl_utl[link_num-1]
  259.     struct ce_dtl_utl_reg {
  260.         /* DTL */
  261.         u64    ce_dtl_dtdr_credit_limit;    /* 0x00y000 */
  262.         u64    ce_dtl_dtdr_credit_force;    /* 0x00y008 */
  263.         u64    ce_dtl_dyn_credit_status;    /* 0x00y010 */
  264.         u64    ce_dtl_dtl_last_credit_stat;    /* 0x00y018 */
  265.         u64    ce_dtl_dtl_ctrl;        /* 0x00y020 */
  266.         u64    ce_pad_00y028[5];   /* 0x00y028 -- 0x00y048 */
  267.         u64    ce_dtl_debug_sel;        /* 0x00y050 */
  268.         u64    ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
  269.  
  270.         /* UTL */
  271.         u64    ce_utl_utl_ctrl;        /* 0x00z000 */
  272.         u64    ce_utl_debug_sel;        /* 0x00z008 */
  273.         u64    ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
  274.     } ce_dtl_utl[2];
  275.  
  276.     u64    ce_pad_00A000[514];        /* 0x00A000 -- 0x00B008 */
  277.  
  278.     /*
  279.      * URE: Upstream Request Engine
  280.          */
  281.     u64    ce_ure_dyn_credit_status;        /* 0x00B010 */
  282.     u64    ce_ure_last_credit_status;        /* 0x00B018 */
  283.     u64    ce_ure_credit_limit;            /* 0x00B020 */
  284.     u64    ce_pad_00B028;                /* 0x00B028 */
  285.     u64    ce_ure_control;                /* 0x00B030 */
  286.     u64    ce_ure_status;                /* 0x00B038 */
  287.     u64    ce_pad_00B040[2];        /* 0x00B040 -- 0x00B048 */
  288.     u64    ce_ure_debug_sel;            /* 0x00B050 */
  289.     u64    ce_ure_pcie_debug_sel;            /* 0x00B058 */
  290.     u64    ce_ure_ssp_err_cmd_wrd;            /* 0x00B060 */
  291.     u64    ce_ure_ssp_err_addr;            /* 0x00B068 */
  292.     u64    ce_ure_page_map;            /* 0x00B070 */
  293.     u64    ce_ure_dir_map[TIOCE_NUM_PORTS];    /* 0x00B078 */
  294.     u64    ce_ure_pipe_sel1;            /* 0x00B088 */
  295.     u64    ce_ure_pipe_mask1;            /* 0x00B090 */
  296.     u64    ce_ure_pipe_sel2;            /* 0x00B098 */
  297.     u64    ce_ure_pipe_mask2;            /* 0x00B0A0 */
  298.     u64    ce_ure_pcie1_credits_sent;        /* 0x00B0A8 */
  299.     u64    ce_ure_pcie1_credits_used;        /* 0x00B0B0 */
  300.     u64    ce_ure_pcie1_credit_limit;        /* 0x00B0B8 */
  301.     u64    ce_ure_pcie2_credits_sent;        /* 0x00B0C0 */
  302.     u64    ce_ure_pcie2_credits_used;        /* 0x00B0C8 */
  303.     u64    ce_ure_pcie2_credit_limit;        /* 0x00B0D0 */
  304.     u64    ce_ure_pcie_force_credit;        /* 0x00B0D8 */
  305.     u64    ce_ure_rd_tnum_val;            /* 0x00B0E0 */
  306.     u64    ce_ure_rd_tnum_rsp_rcvd;        /* 0x00B0E8 */
  307.     u64    ce_ure_rd_tnum_esent_timer;        /* 0x00B0F0 */
  308.     u64    ce_ure_rd_tnum_error;            /* 0x00B0F8 */
  309.     u64    ce_ure_rd_tnum_first_cl;        /* 0x00B100 */
  310.     u64    ce_ure_rd_tnum_link_buf;        /* 0x00B108 */
  311.     u64    ce_ure_wr_tnum_val;            /* 0x00B110 */
  312.     u64    ce_ure_sram_err_addr0;            /* 0x00B118 */
  313.     u64    ce_ure_sram_err_addr1;            /* 0x00B120 */
  314.     u64    ce_ure_sram_err_addr2;            /* 0x00B128 */
  315.     u64    ce_ure_sram_rd_addr0;            /* 0x00B130 */
  316.     u64    ce_ure_sram_rd_addr1;            /* 0x00B138 */
  317.     u64    ce_ure_sram_rd_addr2;            /* 0x00B140 */
  318.     u64    ce_ure_sram_wr_addr0;            /* 0x00B148 */
  319.     u64    ce_ure_sram_wr_addr1;            /* 0x00B150 */
  320.     u64    ce_ure_sram_wr_addr2;            /* 0x00B158 */
  321.     u64    ce_ure_buf_flush10;            /* 0x00B160 */
  322.     u64    ce_ure_buf_flush11;            /* 0x00B168 */
  323.     u64    ce_ure_buf_flush12;            /* 0x00B170 */
  324.     u64    ce_ure_buf_flush13;            /* 0x00B178 */
  325.     u64    ce_ure_buf_flush20;            /* 0x00B180 */
  326.     u64    ce_ure_buf_flush21;            /* 0x00B188 */
  327.     u64    ce_ure_buf_flush22;            /* 0x00B190 */
  328.     u64    ce_ure_buf_flush23;            /* 0x00B198 */
  329.     u64    ce_ure_pcie_control1;            /* 0x00B1A0 */
  330.     u64    ce_ure_pcie_control2;            /* 0x00B1A8 */
  331.  
  332.     u64    ce_pad_00B1B0[458];        /* 0x00B1B0 -- 0x00BFF8 */
  333.  
  334.     /* Upstream Data Buffer, Port1 */
  335.     struct ce_ure_maint_ups_dat1_data {
  336.         u64    data63_0[512];        /* 0x00C000 -- 0x00CFF8 */
  337.         u64    data127_64[512];    /* 0x00D000 -- 0x00DFF8 */
  338.         u64    parity[512];        /* 0x00E000 -- 0x00EFF8 */
  339.     } ce_ure_maint_ups_dat1;
  340.  
  341.     /* Upstream Header Buffer, Port1 */
  342.     struct ce_ure_maint_ups_hdr1_data {
  343.         u64    data63_0[512];        /* 0x00F000 -- 0x00FFF8 */
  344.         u64    data127_64[512];    /* 0x010000 -- 0x010FF8 */
  345.         u64    parity[512];        /* 0x011000 -- 0x011FF8 */
  346.     } ce_ure_maint_ups_hdr1;
  347.  
  348.     /* Upstream Data Buffer, Port2 */
  349.     struct ce_ure_maint_ups_dat2_data {
  350.         u64    data63_0[512];        /* 0x012000 -- 0x012FF8 */
  351.         u64    data127_64[512];    /* 0x013000 -- 0x013FF8 */
  352.         u64    parity[512];        /* 0x014000 -- 0x014FF8 */
  353.     } ce_ure_maint_ups_dat2;
  354.  
  355.     /* Upstream Header Buffer, Port2 */
  356.     struct ce_ure_maint_ups_hdr2_data {
  357.         u64    data63_0[512];        /* 0x015000 -- 0x015FF8 */
  358.         u64    data127_64[512];    /* 0x016000 -- 0x016FF8 */
  359.         u64    parity[512];        /* 0x017000 -- 0x017FF8 */
  360.     } ce_ure_maint_ups_hdr2;
  361.  
  362.     /* Downstream Data Buffer */
  363.     struct ce_ure_maint_dns_dat_data {
  364.         u64    data63_0[512];        /* 0x018000 -- 0x018FF8 */
  365.         u64    data127_64[512];    /* 0x019000 -- 0x019FF8 */
  366.         u64    parity[512];        /* 0x01A000 -- 0x01AFF8 */
  367.     } ce_ure_maint_dns_dat;
  368.  
  369.     /* Downstream Header Buffer */
  370.     struct    ce_ure_maint_dns_hdr_data {
  371.         u64    data31_0[64];        /* 0x01B000 -- 0x01B1F8 */
  372.         u64    data95_32[64];        /* 0x01B200 -- 0x01B3F8 */
  373.         u64    parity[64];        /* 0x01B400 -- 0x01B5F8 */
  374.     } ce_ure_maint_dns_hdr;
  375.  
  376.     /* RCI Buffer Data */
  377.     struct    ce_ure_maint_rci_data {
  378.         u64    data41_0[64];        /* 0x01B600 -- 0x01B7F8 */
  379.         u64    data69_42[64];        /* 0x01B800 -- 0x01B9F8 */
  380.     } ce_ure_maint_rci;
  381.  
  382.     /* Response Queue */
  383.     u64    ce_ure_maint_rspq[64];        /* 0x01BA00 -- 0x01BBF8 */
  384.  
  385.     u64    ce_pad_01C000[4224];        /* 0x01BC00 -- 0x023FF8 */
  386.  
  387.     /* Admin Build-a-Packet Buffer */
  388.     struct    ce_adm_maint_bap_buf_data {
  389.         u64    data63_0[258];        /* 0x024000 -- 0x024808 */
  390.         u64    data127_64[258];    /* 0x024810 -- 0x025018 */
  391.         u64    parity[258];        /* 0x025020 -- 0x025828 */
  392.     } ce_adm_maint_bap_buf;
  393.  
  394.     u64    ce_pad_025830[5370];        /* 0x025830 -- 0x02FFF8 */
  395.  
  396.     /* URE: 40bit PMU ATE Buffer */            /* 0x030000 -- 0x037FF8 */
  397.     u64    ce_ure_ate40[TIOCE_NUM_M40_ATES];
  398.  
  399.     /* URE: 32/40bit PMU ATE Buffer */        /* 0x038000 -- 0x03BFF8 */
  400.     u64    ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
  401.  
  402.     u64    ce_pad_03C000[2050];        /* 0x03C000 -- 0x040008 */
  403.  
  404.     /*
  405.      * DRE: Down Stream Request Engine
  406.          */
  407.     u64    ce_dre_dyn_credit_status1;        /* 0x040010 */
  408.     u64    ce_dre_dyn_credit_status2;        /* 0x040018 */
  409.     u64    ce_dre_last_credit_status1;        /* 0x040020 */
  410.     u64    ce_dre_last_credit_status2;        /* 0x040028 */
  411.     u64    ce_dre_credit_limit1;            /* 0x040030 */
  412.     u64    ce_dre_credit_limit2;            /* 0x040038 */
  413.     u64    ce_dre_force_credit1;            /* 0x040040 */
  414.     u64    ce_dre_force_credit2;            /* 0x040048 */
  415.     u64    ce_dre_debug_mux1;            /* 0x040050 */
  416.     u64    ce_dre_debug_mux2;            /* 0x040058 */
  417.     u64    ce_dre_ssp_err_cmd_wrd;            /* 0x040060 */
  418.     u64    ce_dre_ssp_err_addr;            /* 0x040068 */
  419.     u64    ce_dre_comp_err_cmd_wrd;        /* 0x040070 */
  420.     u64    ce_dre_comp_err_addr;            /* 0x040078 */
  421.     u64    ce_dre_req_status;            /* 0x040080 */
  422.     u64    ce_dre_config1;                /* 0x040088 */
  423.     u64    ce_dre_config2;                /* 0x040090 */
  424.     u64    ce_dre_config_req_status;        /* 0x040098 */
  425.     u64    ce_pad_0400A0[12];        /* 0x0400A0 -- 0x0400F8 */
  426.     u64    ce_dre_dyn_fifo;            /* 0x040100 */
  427.     u64    ce_pad_040108[3];        /* 0x040108 -- 0x040118 */
  428.     u64    ce_dre_last_fifo;            /* 0x040120 */
  429.  
  430.     u64    ce_pad_040128[27];        /* 0x040128 -- 0x0401F8 */
  431.  
  432.     /* DRE Downstream Head Queue */
  433.     struct    ce_dre_maint_ds_head_queue {
  434.         u64    data63_0[32];        /* 0x040200 -- 0x0402F8 */
  435.         u64    data127_64[32];        /* 0x040300 -- 0x0403F8 */
  436.         u64    parity[32];        /* 0x040400 -- 0x0404F8 */
  437.     } ce_dre_maint_ds_head_q;
  438.  
  439.     u64    ce_pad_040500[352];        /* 0x040500 -- 0x040FF8 */
  440.  
  441.     /* DRE Downstream Data Queue */
  442.     struct    ce_dre_maint_ds_data_queue {
  443.         u64    data63_0[256];        /* 0x041000 -- 0x0417F8 */
  444.         u64    ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
  445.         u64    data127_64[256];    /* 0x042000 -- 0x0427F8 */
  446.         u64    ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
  447.         u64    parity[256];        /* 0x043000 -- 0x0437F8 */
  448.         u64    ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
  449.     } ce_dre_maint_ds_data_q;
  450.  
  451.     /* DRE URE Upstream Response Queue */
  452.     struct    ce_dre_maint_ure_us_rsp_queue {
  453.         u64    data63_0[8];        /* 0x044000 -- 0x044038 */
  454.         u64    ce_pad_044040[24];  /* 0x044040 -- 0x0440F8 */
  455.         u64    data127_64[8];      /* 0x044100 -- 0x044138 */
  456.         u64    ce_pad_044140[24];  /* 0x044140 -- 0x0441F8 */
  457.         u64    parity[8];        /* 0x044200 -- 0x044238 */
  458.         u64    ce_pad_044240[24];  /* 0x044240 -- 0x0442F8 */
  459.     } ce_dre_maint_ure_us_rsp_q;
  460.  
  461.     u64     ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
  462.  
  463.     u64    ce_end_of_struct;            /* 0x044400 */
  464. } tioce_t;
  465.  
  466. /* ce_lsiX_gb_cfg1 register bit masks & shifts */
  467. #define CE_LSI_GB_CFG1_RXL0S_THS_SHFT    0
  468. #define CE_LSI_GB_CFG1_RXL0S_THS_MASK    (0xffULL << 0)
  469. #define CE_LSI_GB_CFG1_RXL0S_SMP_SHFT    8
  470. #define CE_LSI_GB_CFG1_RXL0S_SMP_MASK    (0xfULL << 8);
  471. #define CE_LSI_GB_CFG1_RXL0S_ADJ_SHFT    12
  472. #define CE_LSI_GB_CFG1_RXL0S_ADJ_MASK    (0x7ULL << 12)
  473. #define CE_LSI_GB_CFG1_RXL0S_FLT_SHFT    15
  474. #define CE_LSI_GB_CFG1_RXL0S_FLT_MASK    (0x1ULL << 15)
  475. #define CE_LSI_GB_CFG1_LPBK_SEL_SHFT    16
  476. #define CE_LSI_GB_CFG1_LPBK_SEL_MASK    (0x3ULL << 16)
  477. #define CE_LSI_GB_CFG1_LPBK_EN_SHFT    18
  478. #define CE_LSI_GB_CFG1_LPBK_EN_MASK    (0x1ULL << 18)
  479. #define CE_LSI_GB_CFG1_RVRS_LB_SHFT    19
  480. #define CE_LSI_GB_CFG1_RVRS_LB_MASK    (0x1ULL << 19)
  481. #define CE_LSI_GB_CFG1_RVRS_CLK_SHFT    20
  482. #define CE_LSI_GB_CFG1_RVRS_CLK_MASK    (0x3ULL << 20)
  483. #define CE_LSI_GB_CFG1_SLF_TS_SHFT    24
  484. #define CE_LSI_GB_CFG1_SLF_TS_MASK    (0xfULL << 24)
  485.  
  486. /* ce_adm_int_mask/ce_adm_int_status register bit defines */
  487. #define CE_ADM_INT_CE_ERROR_SHFT        0
  488. #define CE_ADM_INT_LSI1_IP_ERROR_SHFT        1
  489. #define CE_ADM_INT_LSI2_IP_ERROR_SHFT        2
  490. #define CE_ADM_INT_PCIE_ERROR_SHFT        3
  491. #define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT    4
  492. #define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT    5
  493. #define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT    6
  494. #define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT    7
  495. #define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT    8
  496. #define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT    9
  497. #define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT    10
  498. #define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT    11
  499. #define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT    12
  500. #define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT    13
  501. #define CE_ADM_INT_PCIE_MSG_SHFT        14 /*see int_dest_14*/
  502. #define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT        14
  503. #define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT        15
  504. #define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT        16
  505. #define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT        17
  506. #define CE_ADM_INT_PORT1_PM_PME_MSG_SHFT    22
  507. #define CE_ADM_INT_PORT2_PM_PME_MSG_SHFT    23
  508.  
  509. /* ce_adm_force_int register bit defines */
  510. #define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT    0
  511. #define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT    1
  512. #define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT    2
  513. #define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT    3
  514. #define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT    4
  515. #define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT    5
  516. #define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT    6
  517. #define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT    7
  518. #define CE_ADM_FORCE_INT_ALWAYS_SHFT        8
  519.  
  520. /* ce_adm_int_dest register bit masks & shifts */
  521. #define INTR_VECTOR_SHFT            56
  522.  
  523. /* ce_adm_error_mask and ce_adm_error_summary register bit masks */
  524. #define CE_ADM_ERR_CRM_SSP_REQ_INVALID            (0x1ULL <<  0)
  525. #define CE_ADM_ERR_SSP_REQ_HEADER            (0x1ULL <<  1)
  526. #define CE_ADM_ERR_SSP_RSP_HEADER            (0x1ULL <<  2)
  527. #define CE_ADM_ERR_SSP_PROTOCOL_ERROR            (0x1ULL <<  3)
  528. #define CE_ADM_ERR_SSP_SBE                (0x1ULL <<  4)
  529. #define CE_ADM_ERR_SSP_MBE                (0x1ULL <<  5)
  530. #define CE_ADM_ERR_CXM_CREDIT_OFLOW            (0x1ULL <<  6)
  531. #define CE_ADM_ERR_DRE_SSP_REQ_INVAL            (0x1ULL <<  7)
  532. #define CE_ADM_ERR_SSP_REQ_LONG                (0x1ULL <<  8)
  533. #define CE_ADM_ERR_SSP_REQ_OFLOW            (0x1ULL <<  9)
  534. #define CE_ADM_ERR_SSP_REQ_SHORT            (0x1ULL << 10)
  535. #define CE_ADM_ERR_SSP_REQ_SIDEBAND            (0x1ULL << 11)
  536. #define CE_ADM_ERR_SSP_REQ_ADDR_ERR            (0x1ULL << 12)
  537. #define CE_ADM_ERR_SSP_REQ_BAD_BE            (0x1ULL << 13)
  538. #define CE_ADM_ERR_PCIE_COMPL_TIMEOUT            (0x1ULL << 14)
  539. #define CE_ADM_ERR_PCIE_UNEXP_COMPL            (0x1ULL << 15)
  540. #define CE_ADM_ERR_PCIE_ERR_COMPL            (0x1ULL << 16)
  541. #define CE_ADM_ERR_DRE_CREDIT_OFLOW            (0x1ULL << 17)
  542. #define CE_ADM_ERR_DRE_SRAM_PE                (0x1ULL << 18)
  543. #define CE_ADM_ERR_SSP_RSP_INVALID            (0x1ULL << 19)
  544. #define CE_ADM_ERR_SSP_RSP_LONG                (0x1ULL << 20)
  545. #define CE_ADM_ERR_SSP_RSP_SHORT            (0x1ULL << 21)
  546. #define CE_ADM_ERR_SSP_RSP_SIDEBAND            (0x1ULL << 22)
  547. #define CE_ADM_ERR_URE_SSP_RSP_UNEXP            (0x1ULL << 23)
  548. #define CE_ADM_ERR_URE_SSP_WR_REQ_TIMEOUT        (0x1ULL << 24)
  549. #define CE_ADM_ERR_URE_SSP_RD_REQ_TIMEOUT        (0x1ULL << 25)
  550. #define CE_ADM_ERR_URE_ATE3240_PAGE_FAULT        (0x1ULL << 26)
  551. #define CE_ADM_ERR_URE_ATE40_PAGE_FAULT            (0x1ULL << 27)
  552. #define CE_ADM_ERR_URE_CREDIT_OFLOW            (0x1ULL << 28)
  553. #define CE_ADM_ERR_URE_SRAM_PE                (0x1ULL << 29)
  554. #define CE_ADM_ERR_ADM_SSP_RSP_UNEXP            (0x1ULL << 30)
  555. #define CE_ADM_ERR_ADM_SSP_REQ_TIMEOUT            (0x1ULL << 31)
  556. #define CE_ADM_ERR_MMR_ACCESS_ERROR            (0x1ULL << 32)
  557. #define CE_ADM_ERR_MMR_ADDR_ERROR            (0x1ULL << 33)
  558. #define CE_ADM_ERR_ADM_CREDIT_OFLOW            (0x1ULL << 34)
  559. #define CE_ADM_ERR_ADM_SRAM_PE                (0x1ULL << 35)
  560. #define CE_ADM_ERR_DTL1_MIN_PDATA_CREDIT_ERR        (0x1ULL << 36)
  561. #define CE_ADM_ERR_DTL1_INF_COMPL_CRED_UPDT_ERR        (0x1ULL << 37)
  562. #define CE_ADM_ERR_DTL1_INF_POSTED_CRED_UPDT_ERR    (0x1ULL << 38)
  563. #define CE_ADM_ERR_DTL1_INF_NPOSTED_CRED_UPDT_ERR    (0x1ULL << 39)
  564. #define CE_ADM_ERR_DTL1_COMP_HD_CRED_MAX_ERR        (0x1ULL << 40)
  565. #define CE_ADM_ERR_DTL1_COMP_D_CRED_MAX_ERR        (0x1ULL << 41)
  566. #define CE_ADM_ERR_DTL1_NPOSTED_HD_CRED_MAX_ERR        (0x1ULL << 42)
  567. #define CE_ADM_ERR_DTL1_NPOSTED_D_CRED_MAX_ERR        (0x1ULL << 43)
  568. #define CE_ADM_ERR_DTL1_POSTED_HD_CRED_MAX_ERR        (0x1ULL << 44)
  569. #define CE_ADM_ERR_DTL1_POSTED_D_CRED_MAX_ERR        (0x1ULL << 45)
  570. #define CE_ADM_ERR_DTL2_MIN_PDATA_CREDIT_ERR        (0x1ULL << 46)
  571. #define CE_ADM_ERR_DTL2_INF_COMPL_CRED_UPDT_ERR        (0x1ULL << 47)
  572. #define CE_ADM_ERR_DTL2_INF_POSTED_CRED_UPDT_ERR    (0x1ULL << 48)
  573. #define CE_ADM_ERR_DTL2_INF_NPOSTED_CRED_UPDT_ERR    (0x1ULL << 49)
  574. #define CE_ADM_ERR_DTL2_COMP_HD_CRED_MAX_ERR        (0x1ULL << 50)
  575. #define CE_ADM_ERR_DTL2_COMP_D_CRED_MAX_ERR        (0x1ULL << 51)
  576. #define CE_ADM_ERR_DTL2_NPOSTED_HD_CRED_MAX_ERR        (0x1ULL << 52)
  577. #define CE_ADM_ERR_DTL2_NPOSTED_D_CRED_MAX_ERR        (0x1ULL << 53)
  578. #define CE_ADM_ERR_DTL2_POSTED_HD_CRED_MAX_ERR        (0x1ULL << 54)
  579. #define CE_ADM_ERR_DTL2_POSTED_D_CRED_MAX_ERR        (0x1ULL << 55)
  580. #define CE_ADM_ERR_PORT1_PCIE_COR_ERR            (0x1ULL << 56)
  581. #define CE_ADM_ERR_PORT1_PCIE_NFAT_ERR            (0x1ULL << 57)
  582. #define CE_ADM_ERR_PORT1_PCIE_FAT_ERR            (0x1ULL << 58)
  583. #define CE_ADM_ERR_PORT2_PCIE_COR_ERR            (0x1ULL << 59)
  584. #define CE_ADM_ERR_PORT2_PCIE_NFAT_ERR            (0x1ULL << 60)
  585. #define CE_ADM_ERR_PORT2_PCIE_FAT_ERR            (0x1ULL << 61)
  586.  
  587. /* ce_adm_ure_ups_buf_barrier_flush register bit masks and shifts */
  588. #define FLUSH_SEL_PORT1_PIPE0_SHFT    0
  589. #define FLUSH_SEL_PORT1_PIPE1_SHFT    4
  590. #define FLUSH_SEL_PORT1_PIPE2_SHFT    8
  591. #define FLUSH_SEL_PORT1_PIPE3_SHFT    12
  592. #define FLUSH_SEL_PORT2_PIPE0_SHFT    16
  593. #define FLUSH_SEL_PORT2_PIPE1_SHFT    20
  594. #define FLUSH_SEL_PORT2_PIPE2_SHFT    24
  595. #define FLUSH_SEL_PORT2_PIPE3_SHFT    28
  596.  
  597. /* ce_dre_config1 register bit masks and shifts */
  598. #define CE_DRE_RO_ENABLE        (0x1ULL << 0)
  599. #define CE_DRE_DYN_RO_ENABLE        (0x1ULL << 1)
  600. #define CE_DRE_SUP_CONFIG_COMP_ERROR    (0x1ULL << 2)
  601. #define CE_DRE_SUP_IO_COMP_ERROR    (0x1ULL << 3)
  602. #define CE_DRE_ADDR_MODE_SHFT        4
  603.  
  604. /* ce_dre_config_req_status register bit masks */
  605. #define CE_DRE_LAST_CONFIG_COMPLETION    (0x7ULL << 0)
  606. #define CE_DRE_DOWNSTREAM_CONFIG_ERROR    (0x1ULL << 3)
  607. #define CE_DRE_CONFIG_COMPLETION_VALID    (0x1ULL << 4)
  608. #define CE_DRE_CONFIG_REQUEST_ACTIVE    (0x1ULL << 5)
  609.  
  610. /* ce_ure_control register bit masks & shifts */
  611. #define CE_URE_RD_MRG_ENABLE        (0x1ULL << 0)
  612. #define CE_URE_WRT_MRG_ENABLE1        (0x1ULL << 4)
  613. #define CE_URE_WRT_MRG_ENABLE2        (0x1ULL << 5)
  614. #define CE_URE_WRT_MRG_TIMER_SHFT    12
  615. #define CE_URE_WRT_MRG_TIMER_MASK    (0x7FFULL << CE_URE_WRT_MRG_TIMER_SHFT)
  616. #define CE_URE_WRT_MRG_TIMER(x)        (((u64)(x) << \
  617.                       CE_URE_WRT_MRG_TIMER_SHFT) & \
  618.                      CE_URE_WRT_MRG_TIMER_MASK)
  619. #define CE_URE_RSPQ_BYPASS_DISABLE    (0x1ULL << 24)
  620. #define CE_URE_UPS_DAT1_PAR_DISABLE    (0x1ULL << 32)
  621. #define CE_URE_UPS_HDR1_PAR_DISABLE    (0x1ULL << 33)
  622. #define CE_URE_UPS_DAT2_PAR_DISABLE    (0x1ULL << 34)
  623. #define CE_URE_UPS_HDR2_PAR_DISABLE    (0x1ULL << 35)
  624. #define CE_URE_ATE_PAR_DISABLE        (0x1ULL << 36)
  625. #define CE_URE_RCI_PAR_DISABLE        (0x1ULL << 37)
  626. #define CE_URE_RSPQ_PAR_DISABLE        (0x1ULL << 38)
  627. #define CE_URE_DNS_DAT_PAR_DISABLE    (0x1ULL << 39)
  628. #define CE_URE_DNS_HDR_PAR_DISABLE    (0x1ULL << 40)
  629. #define CE_URE_MALFORM_DISABLE        (0x1ULL << 44)
  630. #define CE_URE_UNSUP_DISABLE        (0x1ULL << 45)
  631.  
  632. /* ce_ure_page_map register bit masks & shifts */
  633. #define CE_URE_ATE3240_ENABLE        (0x1ULL << 0)
  634. #define CE_URE_ATE40_ENABLE         (0x1ULL << 1)
  635. #define CE_URE_PAGESIZE_SHFT        4
  636. #define CE_URE_PAGESIZE_MASK        (0x7ULL << CE_URE_PAGESIZE_SHFT)
  637. #define CE_URE_4K_PAGESIZE        (0x0ULL << CE_URE_PAGESIZE_SHFT)
  638. #define CE_URE_16K_PAGESIZE        (0x1ULL << CE_URE_PAGESIZE_SHFT)
  639. #define CE_URE_64K_PAGESIZE        (0x2ULL << CE_URE_PAGESIZE_SHFT)
  640. #define CE_URE_128K_PAGESIZE        (0x3ULL << CE_URE_PAGESIZE_SHFT)
  641. #define CE_URE_256K_PAGESIZE        (0x4ULL << CE_URE_PAGESIZE_SHFT)
  642.  
  643. /* ce_ure_pipe_sel register bit masks & shifts */
  644. #define PKT_TRAFIC_SHRT            16
  645. #define BUS_SRC_ID_SHFT            8
  646. #define DEV_SRC_ID_SHFT            3
  647. #define FNC_SRC_ID_SHFT            0
  648. #define CE_URE_TC_MASK            (0x07ULL << PKT_TRAFIC_SHRT)
  649. #define CE_URE_BUS_MASK            (0xFFULL << BUS_SRC_ID_SHFT)
  650. #define CE_URE_DEV_MASK            (0x1FULL << DEV_SRC_ID_SHFT)
  651. #define CE_URE_FNC_MASK            (0x07ULL << FNC_SRC_ID_SHFT)
  652. #define CE_URE_PIPE_BUS(b)        (((u64)(b) << BUS_SRC_ID_SHFT) & \
  653.                      CE_URE_BUS_MASK)
  654. #define CE_URE_PIPE_DEV(d)        (((u64)(d) << DEV_SRC_ID_SHFT) & \
  655.                      CE_URE_DEV_MASK)
  656. #define CE_URE_PIPE_FNC(f)        (((u64)(f) << FNC_SRC_ID_SHFT) & \
  657.                      CE_URE_FNC_MASK)
  658.  
  659. #define CE_URE_SEL1_SHFT        0
  660. #define CE_URE_SEL2_SHFT        20
  661. #define CE_URE_SEL3_SHFT        40
  662. #define CE_URE_SEL1_MASK        (0x7FFFFULL << CE_URE_SEL1_SHFT)
  663. #define CE_URE_SEL2_MASK        (0x7FFFFULL << CE_URE_SEL2_SHFT)
  664. #define CE_URE_SEL3_MASK        (0x7FFFFULL << CE_URE_SEL3_SHFT)
  665.  
  666.  
  667. /* ce_ure_pipe_mask register bit masks & shifts */
  668. #define CE_URE_MASK1_SHFT        0
  669. #define CE_URE_MASK2_SHFT        20
  670. #define CE_URE_MASK3_SHFT        40
  671. #define CE_URE_MASK1_MASK        (0x7FFFFULL << CE_URE_MASK1_SHFT)
  672. #define CE_URE_MASK2_MASK        (0x7FFFFULL << CE_URE_MASK2_SHFT)
  673. #define CE_URE_MASK3_MASK        (0x7FFFFULL << CE_URE_MASK3_SHFT)
  674.  
  675.  
  676. /* ce_ure_pcie_control1 register bit masks & shifts */
  677. #define CE_URE_SI            (0x1ULL << 0)
  678. #define CE_URE_ELAL_SHFT        4
  679. #define CE_URE_ELAL_MASK        (0x7ULL << CE_URE_ELAL_SHFT)
  680. #define CE_URE_ELAL_SET(n)        (((u64)(n) << CE_URE_ELAL_SHFT) & \
  681.                      CE_URE_ELAL_MASK)
  682. #define CE_URE_ELAL1_SHFT        8
  683. #define CE_URE_ELAL1_MASK        (0x7ULL << CE_URE_ELAL1_SHFT)
  684. #define CE_URE_ELAL1_SET(n)        (((u64)(n) << CE_URE_ELAL1_SHFT) & \
  685.                      CE_URE_ELAL1_MASK)
  686. #define CE_URE_SCC            (0x1ULL << 12)
  687. #define CE_URE_PN1_SHFT            16
  688. #define CE_URE_PN1_MASK            (0xFFULL << CE_URE_PN1_SHFT)
  689. #define CE_URE_PN2_SHFT            24
  690. #define CE_URE_PN2_MASK            (0xFFULL << CE_URE_PN2_SHFT)
  691. #define CE_URE_PN1_SET(n)        (((u64)(n) << CE_URE_PN1_SHFT) & \
  692.                      CE_URE_PN1_MASK)
  693. #define CE_URE_PN2_SET(n)        (((u64)(n) << CE_URE_PN2_SHFT) & \
  694.                      CE_URE_PN2_MASK)
  695.  
  696. /* ce_ure_pcie_control2 register bit masks & shifts */
  697. #define CE_URE_ABP            (0x1ULL << 0)
  698. #define CE_URE_PCP            (0x1ULL << 1)
  699. #define CE_URE_MSP            (0x1ULL << 2)
  700. #define CE_URE_AIP            (0x1ULL << 3)
  701. #define CE_URE_PIP            (0x1ULL << 4)
  702. #define CE_URE_HPS            (0x1ULL << 5)
  703. #define CE_URE_HPC            (0x1ULL << 6)
  704. #define CE_URE_SPLV_SHFT        7
  705. #define CE_URE_SPLV_MASK        (0xFFULL << CE_URE_SPLV_SHFT)
  706. #define CE_URE_SPLV_SET(n)        (((u64)(n) << CE_URE_SPLV_SHFT) & \
  707.                      CE_URE_SPLV_MASK)
  708. #define CE_URE_SPLS_SHFT        15
  709. #define CE_URE_SPLS_MASK        (0x3ULL << CE_URE_SPLS_SHFT)
  710. #define CE_URE_SPLS_SET(n)        (((u64)(n) << CE_URE_SPLS_SHFT) & \
  711.                      CE_URE_SPLS_MASK)
  712. #define CE_URE_PSN1_SHFT        19
  713. #define CE_URE_PSN1_MASK        (0x1FFFULL << CE_URE_PSN1_SHFT)
  714. #define CE_URE_PSN2_SHFT        32
  715. #define CE_URE_PSN2_MASK        (0x1FFFULL << CE_URE_PSN2_SHFT)
  716. #define CE_URE_PSN1_SET(n)        (((u64)(n) << CE_URE_PSN1_SHFT) & \
  717.                      CE_URE_PSN1_MASK)
  718. #define CE_URE_PSN2_SET(n)        (((u64)(n) << CE_URE_PSN2_SHFT) & \
  719.                      CE_URE_PSN2_MASK)
  720.  
  721. /*
  722.  * PIO address space ranges for CE
  723.  */
  724.  
  725. /* Local CE Registers Space */
  726. #define CE_PIO_MMR            0x00000000
  727. #define CE_PIO_MMR_LEN            0x04000000
  728.  
  729. /* PCI Compatible Config Space */
  730. #define CE_PIO_CONFIG_SPACE        0x04000000
  731. #define CE_PIO_CONFIG_SPACE_LEN        0x04000000
  732.  
  733. /* PCI I/O Space Alias */
  734. #define CE_PIO_IO_SPACE_ALIAS        0x08000000
  735. #define CE_PIO_IO_SPACE_ALIAS_LEN    0x08000000
  736.  
  737. /* PCI Enhanced Config Space */
  738. #define CE_PIO_E_CONFIG_SPACE        0x10000000
  739. #define CE_PIO_E_CONFIG_SPACE_LEN    0x10000000
  740.  
  741. /* PCI I/O Space */
  742. #define CE_PIO_IO_SPACE            0x100000000
  743. #define CE_PIO_IO_SPACE_LEN        0x100000000
  744.  
  745. /* PCI MEM Space */
  746. #define CE_PIO_MEM_SPACE        0x200000000
  747. #define CE_PIO_MEM_SPACE_LEN        TIO_HWIN_SIZE
  748.  
  749.  
  750. /*
  751.  * CE PCI Enhanced Config Space shifts & masks
  752.  */
  753. #define CE_E_CONFIG_BUS_SHFT        20
  754. #define CE_E_CONFIG_BUS_MASK        (0xFF << CE_E_CONFIG_BUS_SHFT)
  755. #define CE_E_CONFIG_DEVICE_SHFT        15
  756. #define CE_E_CONFIG_DEVICE_MASK        (0x1F << CE_E_CONFIG_DEVICE_SHFT)
  757. #define CE_E_CONFIG_FUNC_SHFT        12
  758. #define CE_E_CONFIG_FUNC_MASK        (0x7  << CE_E_CONFIG_FUNC_SHFT)
  759.  
  760. #endif /* __ASM_IA64_SN_TIOCE_H__ */
  761.