ocr: Hardware-based Memory Disambiguation Core TM Microarchitecture Other INSI2LGAD yE INSTe 2 LOAD T IN INST I *STORE xF ORDER INST - SORE XI" DECODE/SCHEDULE DECODE/SCHEDULE IINST 2 LOAD LY INST 21 LOAD Lyy INST 1STORE X INSTS 1 STORE EXJM ou HARDWARE OF DRDER Mern. Dis. INST 2 LOADI EYI Predichor EXECUTE STALL INST 1'STORE LXI Inst. 2 Must Wail For Inst. 2"Load" inst. 1Store cCan oseurs INEr - SIORL X TO complete Berore Inst. 1 "Store"