InfoMagic Standards 1993 July

home *** CD-ROM | disk | FTP | other *** search

/ InfoMagic Standards 1993 July / Disc.iso / ccitt / 1992 / g / g704.asc < prev next >

Wrap

Text File | 1993-08-15 | 60.4 KB | 2,663 lines

3. Recommendation G.704 SYNCHRONOUS FRAME STRUCTURES USED AT PRIMARY AND SECONDARY HIERARCHICAL LEVELS 1. General This Recommendation gives functional characteristics of interfaces asso- ciated with: - network nodes, in particular, synchronous digital multiplex equip- ment and digital exchanges in IDNs for telephony and ISDNs, and - PCM multiplexing equipment. Section 2 deals with basic frame structures, including details of frame length, frame alignment signals, cyclic redundancy check procedures and other basic information. Sections 3 to 6 contain more specific information about how certain channels at 64 kbit/s and at other bit rates are accommodated within the basic frame structures described in section 2. Electrical characteristics for these interfaces are defined in Recommen- dation G.703. Note 1 - This Recommendation does not necessarily apply for those cases where the signals that cross the interfaces are devoted to non-switched connections such as those for the transport of encoded wideband signals (e.g. broadcast TV signals or multiplexed sound programme signals which need not be individually routed via the ISDN), see also Annex A to Recommendation G.702. Note 2 - The frame structures recommended in this Recommendation do not apply to certain maintenance signals such as the all ones signals transmitted during fault conditions or other signals transmitted during out-of-service conditions. Note 3 - Frame structures associated with digital multiplexing equip- ments using justification are covered in each corresponding equipment Recommendation. Note 4 - Inclusion of channel structures at other bit rates than 64 kbit/s is a matter for further study. Recommendations G.761 and G.76x dealing with the characteristics of PCM/ADPCM transcoding equipment contain information about channel structures at 32 kbit/s. The more general use of those particular structures is the subject of further study. 2. Basic frame structures 2.1 Basic frame structure at 1544 kbit/s 2.1.1 Frame length 193 bits, numbered 1 to 193. The frame repetition rate is 8 000 Hz. 2.1.2 F-bit The first bit of a frame is designated an F-bit and is used for such pur- poses as frame alignment, performance monitoring and providing a data link. 2.1.3 Allocation of F-bit Two alternative methods as given in Tables 1/G.704 and 2/G.704 for allo- cation of F-bits are recommended. 2.1.3.1 Methods 1-24 frame multiframe Allocation of the F-bit to the multiframe alignment signal, the CRC check bits and the data link is given in Table 1/G.704. 2.1.3.1.1Multiframe alignment signal The F-bit of every fourth frame forms the pattern 001011...001011. This multiframe alignment signal is used to identify where each particular frame is located within the multiframe in order to extract the cyclic redundancy check code, CRC-6, and the data link information as well as to identify those frames that contain signalling (frames 6, 12, 18 and 24), if channel associated signalling is used. 2.1.3.1.2Cyclic redundancy check The CRC-6 is a method of performance monitoring that is contained within the F-bit position of frames 2, 6, 10, 14, 18 and 22 of every multi- frame (see Table1/G.704). The CRC-6 message block check bits e1, e2, e3, e4, e5 and e6 are con- tained within multiframe bits 194, 966, 1738, 2510, 3282 and 4054 respectively, as shown in Table 1/G.704. The CRC-6 Message Block (CMB) is a sequence of 4632 serial bits that is coincident with a multi- frame. By definition, CMB N begins at bit position 1 of multiframe N and ends at bit position 4632 of multiframe N. The first transmitted CRC bit of a multiframe is the most significant bit of the CMB polynomial. In calculating the CRC-6 bits, the F-bits are replaced by binary ones. All information in the other bit positions will be identical to the information in the corresponding multiframe bit positions. The check-bit sequence e1 through e6 transmitted in multiframe N+1 is the remainder after multiplication by x6 and then division (Modulo-2) by the generator polynomial x6+x+1 of the polynomial corresponding to CMB N. The first check bit (e1) is the most significant bit of the remain- der; the last check bit (e6) is the least significant bit of the remainder. Each multiframe contains the CRC-6 check bits generated for the preced- ing CMB. At the receiver, the received CMB, with each F-bit having first been replaced by a binary one, is acted upon by the multiplication/division process described above. The resulting remainder is compared on a bit- by-bit basis with the CRC-6 check bits contained in the subsequently received multiframe. The compared check bits will be identical in the absence of transmission errors. 2.1.3.1.34 kbit/s data link Beginning with frame 1 of the multiframe (see Table 1/G.704) first bit of a frame is part of the 4 kbit/s data link. This data link provides acommu- nication path between primary hierarchical level terminals and will con- tain data, an idle data link sequence or a loss of frame alignment alarm sequence. The format to be used for the transmission of data over the (m) bits of the data link is still under study. The idle data link pattern is also under study. A loss of frame alignment alarm sequence is used when a loss of frame alignment (LFA) condition has been detected. After a loss of frame align- ment condition is detected at local end A, and 16-bit LFA sequence of 8 "ones" 8 "zeros" (1111111100000000) will be transmitted in the (m) bits of the 4 kbit/s data link continuously to remote end B. TABLE 1/G.704 Multiframe structure for the 24 frame multiframe +ûûûûûûûûûûû+ûûûûûûûûûûûûûûûûûûûûûûûûûûûû+ûûûûûûûûûûûûûûûû ûûûû+ûûûûûûûûûûû+ _ _ _ Bit number(s) in _ _ _ _ F-bit _ in each channel _ _ _ _ _ time slot _ _ _Frame +ûûûûûûûûûûû+ûûûûûûûûûûûûûûûû+ûûûûûûûûû+ûûûûûûûûû û+ûûûûûûûûûûû+ _Number _Bit number_ Assignments _ For* _ For* _Signal- ling*_ _within _within +ûûûûû+ûûûû+ûûûûû+character_signalling_ chan- nel _ _multiframe _multiframe _FAS_DL_CRC_ signal _ _designa- tion_ +ûûûûûûûûûûû+ûûûûûûûûûûû+ûûûûû+ûûûû+ûûûûû+ûûûûûûûûû+ûûûûû ûûûûû+ûûûûûûûûûûû+ _ 1 _ 1 _ - _ m _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 2 _ 194 _ - _ - _ el _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 3 _ 387 _ - _ m _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 4 _ 580 _ 0 _ - _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 5 _ 773 _ - _ m _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 6 _ 966 _ - _ - _ e2 _ 1 - 7 _ 8 _ A _ _ _ _ _ _ _ _ _ _ _ 7 _ 1159 _ - _ m _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 8 _ 1352 _ 0 _ - _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 9 _ 1545 _ - _ m _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 10 _ 1738 _ - _ - _ e3 _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 11 _ 1931 _ - _ m _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 12 _ 2124 _ 1 _ - _ - _ 1 - 7 _ 8 _ B _ _ _ _ _ _ _ _ _ _ _ 13 _ 2317 _ - _ m _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 14 _ 2510 _ - _ - _ e4 _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 15 _ 2703 _ - _ m _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 16 _ 2896 _ 0 _ - _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 17 _ 3089 _ - _ m _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 18 _ 328 _ - _ - _ e5 _ 1 - 7 _ 8 _ C _ _ _ _ _ _ _ _ _ _ _ 19 _ 3475 _ - _ m _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 20 _ 3668 _ 1 _ - _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 21 _ 3861 _ - _ m _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 22 _ 4054 _ - _ - _ e6 _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 23 _ 4247 _ - _ m _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ _ _ 24 _ 42440 _ 1 _ - _ - _ 1-7 _ 8 _ D _ +ûûûûûûûûûûû+ûûûûûûûûûûû+ûûûûû+ûûûû+ûûûûû+ûûûûûûûûû+ûûûûû ûûûûû+ûûûûûûûûûûû+ FAS:Frame Alignment Signal (....001011....) DL:4 kbit/s Data Link (message bits m) CRC:CRC-6 Block Check Field (check bits e1 ... e6) * Only applicable in the case of channel associated signalling, ct. k6 º 3.1.3.2. 2.1.3.2 Method 2 - 12 frame multiframe Allocation of the F-bit to frame alignment signal, multiframe alignment signal and signalling is given in Table2/G.704. TABLE 2/G.704 Allocation of f-bit for the 12 frame multiframe +ûûûûûûûûûûûûûû+ûûûûûûûûûûûûûûûûû+ûûûûûûûûûûûûûûûûûûûûûûû+ _ Frame number _ Frame alignment _ Multiframe alignment _ _ _ signal _ signal or signalling _ +ûûûûûûûûûûûûûû+ûûûûûûûûûûûûûûûûû+ûûûûûûûûûûûûûûûûûûûûûûû+ _ 1 _ 1 _ - _ _ _ _ _ _ 2 _ - _ S _ _ _ _ _ _ 3 _ 0 _ - _ _ _ _ _ _ 4 _ - _ S _ +ûûûûûûûûûûûûûû+ûûûûûûûûûûûûûûûûû+ûûûûûûûûûûûûûûûûûûûûûûû+ Note - For multiframe structure see section 3.1.3.2.2. 2.2 Basic frame structure at 6312 kbit/s 2.2.1 Frame length The number of bits per frame is 789. The frame repetition rate is 8000Hz. 2.2.2 F-bits The last five bits of a frame are designated as F-bits, and are used for such purposes as frame alignment, performance monitoring and provid- ing a data link. 2.2.3 Allocation of F-bits Allocation of the F-bits is given in Table 3/G.704. TABLE 3/G.704 Allocation of F-bits +ûûûûûûûûûûûû+ûûûûûûûûûûûûûûûûûûûûûûûûûûûûûûûûûûûûûûû+ _ _ _ _ _ Bit number _ _Frame number_ _ _ +ûûûûûûû+ûûûûûûû+ûûûûûûû+ûûûûûûû+ûûûûûûû+ _ _ 785 _ 786 _ 787 _ 788 _ 789 _ +ûûûûûûûûûûûû+ûûûûûûû+ûûûûûûû+ûûûûûûû+ûûûûûûû+ûûûûûûû+ _ 1 _ 1 _ 1 _ 0 _ 0 _ m _ _ _ _ _ _ _ _ _ 2 _ 1 _ 0 _ 1 _ 0 _ 0 _ _ _ _ _ _ _ _ _ 3 _ x _ x _ x _ a _ m _ _ _ _ _ _ _ _ _ 4 _ e1 _ e2 _ e3 _ e4 _ e5 _ +ûûûûûûûûûûûû+ûûûûûûû+ûûûûûûû+ûûûûûûû+ûûûûûûû+ûûûûûûû+ m:data link bit a:remote end alarm bit (1 state = alarm, 0 state = no alarm) ei:CRC-5 check bit (i = 1 to 5) x:spare bits to be set at state 1 if not used 2.2.3.1 Frame alignment signal The frame and multiframe alignment signal is:110010100, and is carried on the F-bits in frames 1 and 2, excluding bit 789 of frame 1. 2.2.3.2 Cyclic redundancy check The cyclic redundancy check 5 (CRC-5) message block (CMB) is a sequence of 3151 serial bits which starts at bit number 1 of frame number 1 and ends at bit number 784 of frame number 4. The CRC-5 message block check bits e1, e2, e3, e4 and e5 occupy the last five bits of the mul- tiframe as shown in Table 3/G.704. The check-bit sequence e1 through e5 transmitted in multiframe N is the remainder after multiplication by x5 and division (Modulo-2) by the gen- erator polynomial X5+X4+X2+1 of the polynomial corresponding to CMB N. The first check bit (e1) is the most significant bit of the remain- der; the last check bit (e5) is the least significant bit of the remainder. Each multiframe contains the CRC- 5 check bits generated for the corre- sponding CMB. At the receiver the incoming sequence of 3156 serial bits (i.e.,3151bits of CMB and 5 CRC bits), when divided by the generator polynomials, will result in a remainder of 00000 in the absence of transmission errors. 2.2.3.3 4 kbit/s data link The bit m shown in Table 3/G.704 is used as a data link bit. These bits provide 4 kbit/s data transmission capability associated the 6312 kbit/s digital path. 2.2.3.4 Remote end alarm indication After a loss of frame alignment condition is detected at local end A, remote end alarm signal bit as shown in Table 3/G.704 will be transmit- ted to remote end B. 2.3 Basic frame structure at 2048 kbit/s 2.3.1 Frame length 256 bits, numbered 1 to 256. The frame repetition rate is 8000Hz. 2.3.2 Allocation of bits numbers 1 to 8 of the frame Allocation of bits numbers 1 to 8 of the frame is shown in Table4a/ G.704. TABLE 4a/G.704 Allocation of bits 1 to 8 of the frame +ûûûûûûûûûûûûûûûûûûûûûûûûû+ûûûûûûû+ûûûûûû+ûûûûûû+ûûûûû+ûû ûûû+ûûûû+ûûûû+ûûûû+ _ Bit _ _ _ _ _ _ _ _ _ _ number _ 1 _ 2 _ 3 _ 4 _ 5 _ 6 _ 7 _ 8 _ _ _ _ _ _ _ _ _ _ _ _ Alternate _ _ _ _ _ _ _ _ _ _ frames _ _ _ _ _ _ _ _ _ +ûûûûûûûûûûûûûûûûûûûûûûûûû+ûûûûûûû+ûûûûûû+ûûûûûû+ûûûûû+ûû ûûû+ûûûû+ûûûû+ûûûû+ _ Frame containing _ Si _ 0 _ 0 _ 1 _ 1 _ 0 _ 1 _ 1 _ _ the frame +ûûûûûûû+ûûûûûû+ûûûûûû+ûûûûû+ûûûûû+ûûûû+û ûûû+ûûûû+ _ alignment signal _ Note 1_ Frame alignment signal _ +ûûûûûûûûûûûûûûûûûûûûûûûûû+ûûûûûûû+ûûûûûû+ûûûûûû+ûûûûû+ûû ûûû+ûûûû+ûûûû+ûûûû+ _ Frame not containing _ Si _ 1 _ A _ Sa4 _ Sa5 _Sa6 _Sa7 _Sa8 _ _ the frame alignment +ûûûûûûû+ûûûûûû+ûûûûûû+ûûûûû+ûûûûû+ûûû û+ûûûû+ûûûû+ _ signal _ Note 1_Note 2_Note 3_ Note 4 _ +ûûûûûûûûûûûûûûûûûûûûûûûûû+ûûûûûûû+ûûûûûû+ûûûûûû+ûûûûûûûû ûûûûûûûûûûûûûûûûûû+ Note 1 - Si - Bits reserved for international use. One specific use is described in section2.3.3. Other possible uses may be defined at a later stage. If no use is realized, these bits should be fixed at 1 on digital paths crossing an international border. However, they may be used nationally if the digital path does not cross a border. Note 2 - This bit is fixed at 1 to assist in avoiding simulations of the frame alignment signal. Note 3 - A - Remote alarm indication. In undistributed operation, O; in alarm condition, 1. Note 4 - Sa4 to Sa8 - additional spare bits whose use may be as follows: i) bits Sa4 to Sa8 may be recommended by CCITT for use in specific point-to-point applications (e.g. transcoder equipments conforming to Recommendation G.761); ii) bit Sa4 may be recommended by CCITT as a message-based data link for operations, maintenance and performance monitoring. This channel originates at the point where the frame is generated and termi- nates where the frame is broken down. This requires further study; iii) bits Sa5 to Sa7 are for national usage where there is no demand on them for specific point-to-point applications (see i) above). Bits Sa4 to Sa8 (where these are not used) should be set to "1" on links crossing an international border. 2.3.3 Description of the CRC-4 procedure in bit 1 of the frame 2.3.3.1 Special use of bit 1 of the frame: where there is a need to provide additional protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error monitoring capability, then bit 1 should be used for a Cyclic Redundancy Check-4 (CRC-4) pro- cedure as detailed below. Note - Equipment incorporating the CRC-4 procedure should be designed to be capable of interworking with equipment which does not incorporate the CRC procedure, with the option being manually select- able (e.g., by straps). For such interworking, bit 1 of the frame should be fixed at 1state in both directions (see Table4a/G.704, Note 1). 2.3.3.2 The allocation of bits 1 to 8 of the frame is shown in Table4b/ G.704 for a complete CRC-4 multiframe. TABLE 4B/G.704 CRC-4 multiframe structure +ûûûûûûûûûûûûûûû+ûûûûûûûû+ûûûûûûûûûûûûûûûûûûûûûûûûûû ûûûûûûûûûûûûû+ _ Sub-multiframe_Frame_ Bits 1 to 8 of the frame _ _ (SMF) _number+ûûûû+ûûûû+ûûûû+ûûûû+ûûûû+ûûûû+û ûûû+ûûûû+ _ _ _ 1 _ 2 _ 3 _ 4 _ 5 _ 6 _ 7 _ 8 _ +ûûûûûûûûûûû+ûûûûûûûûûûûûûûû+ûûûûûûûû+ûûûû+ûûûû+ûûûû+ûûûû +ûûûû+ûûûû+ûûûû+ûûûû+ _ _ _ 0 _ C1 _ 0 _ 0 _ 1 _ 1 _ 0 _ 1 _ 1 _ _ _ _ 1 _ 0 _ 1 _ A _Sa4 _Sa5 _Sa6 _Sa7 _Sa8 _ _ _ _ 2 _ C2 _ 0 _ 0 _ 1 _ 1 _ 0 _ 1 _ 1 _ _ _ I _ 3 _ 0 _ 1 _ A _Sa4 _Sa5 _Sa6 _Sa7 _Sa8 _ _ _ _ 4 _ C3 _ 0 _ 0 _ 1 _ 1 _ 0 _ 1 _ 1 _ _ _ _ 5 _ 1 _ 1 _ A _Sa4 _Sa5 _Sa6 _Sa7 _Sa8 _ _ _ _ 6 _ C4 _ 0 _ 0 _ 1 _ 1 _ 0 _ 1 _ 1 _ _ _ _ 7 _ 0 _ 1 _ A _Sa4 _Sa5 _Sa6 _Sa7 _Sa8 _ _Multiframe +ûûûûûûûûûûûûûûû+ûûûûûûûû+ûûûû+ûûûû+ûûûû+ûûûû+û ûûû+ûûûû+ûûûû+ûûûû+ _ _ _ 8 _ C1 _ 0 _ 0 _ 1 _ 1 _ 0 _ 1 _ 1 _ _ _ _ 9 _ 1 _ 1 _ A _Sa4 _Sa5 _Sa6 _Sa7 _Sa8 _ _ _ _ 10 _ C2 _ 0 _ 0 _ 1 _ 1 _ 0 _ 1 _ 1 _ _ _ _ 11 _ 1 _ 1 _ A _Sa4 _Sa5 _Sa6 _Sa7 _Sa8 _ _ _ II _ 12 _ C3 _ 0 _ 0 _ 1 _ 1 _ 0 _ 1 _ 1 _ _ _ _ 13 _ E _ 1 _ A _Sa4 _Sa5 _Sa6 _Sa7 _Sa8 _ _ _ _ 14 _ C4 _ 0 _ 0 _ 1 _ 1 _ 0 _ 1 _ 1 _ _ _ _ 15 _ E _ 1 _ A _Sa4 _Sa5 _Sa6 _Sa7 _Sa8 _ +ûûûûûûûûûûû+ûûûûûûûûûûûûûûû+ûûûûûûûû+ûûûû+ûûûû+ûûûû+ûûûû +ûûûû+ûûûû+ûûûû+ûûûû+ Key:E - CRC-4 error indication bits (see section 2.3.3.4). SA - Spare bits (see Note 4 to Table 4a/G.704). C1, C2, C3, C4 - Cyclic Redundancy Check-4 (CRC-4) bits (see sections 2.3.3.4 and 2.3.3.5). A - remote alarm indication (see Table 4a/G.704). 2.3.3.3 Each CRC-4 multiframe, which is composed of 16 frames num- bered 0 to 15, is divided into two 8 frame sub-multiframes (SMF), desig- nated SMF I and SMFII signifying their respective order of occurrence within the CRC-4 multiframe structure. The SMF is the Cyclic Redun- dancy Check-4 (CRC-4) block size (i.e., 2048 bits). The CRC-4 multiframe structure is not related to the possible use of a multiframe structure in 64 kbit/s channel time slot 16 (see section5.1.3.2). 2.3.3.4 The use of bit 1 in 2048 kbit/s CRC-4 multiframe In those frames containing the frame alignment signal (defined in section2.3.2), bit 1 is used to transmit the CRC-4 bits. There are four CRC-4 bits in each SMF designated C1, C2, C3 and C4. In those frames not containing the frame alignment signal (see section2.3.2), bit 1 is used to transmit the 6-bit CRC-4 multiframe align- ment signal and two spare bits (E). The CRC-4 multiframe alignment signal has the form 001011. The E bits should be used to indicate received errored sub-multiframes by setting the binary state of one E bit from "1" to "0" for each errored sub-multiframe. Any delay between the detection of an errored sub-mul- tiframe and the setting of the E bit that indicates the error state must be less than 1 second. Note 1 - The E bits will always be taken into account even if the SMF which contains them is found to be errored, since there is little likelihood that they will be errored. Note 2 - In the short term, there may exist, equipments which do not use the Si bits; in this case the Si bits are set to binary 1. 2.3.3.5 4 kbit/s Cyclic Redundancy Check 2.3.3.5.1Multiplication/division process A particular CRC-4 word, located in SMF(N) say, is the remainder after multiplication by x4 and then division (modulo 2) by the generator polynomialx4 + x + 1, of the polynomial representation of SMF(N-1). Note - When representing the contents of the check block as a polyno- mial, the first bit in the block i.e., frame 0 bit 1 or frame 8 bit 1 should be taken as being the most significant bit. Similarly, C1 is defined to be the most significant bit of the remain- der and C4 the least significant bit of the remainder. 2.3.3.5.2Encoding procedure i) the CRC-4 bits in the SMF are replaced by binary zeros. ii) The SMF is then acted upon by the multiplication/division process referred to the above section 2.3.3.5.1. iii) The remainder resulting from the multiplication/division process is stored ready for insertion into the respective CRC-4 locations of the next SMF. Note - The CRC-4 bits thus generated do not affect the result of the mul- tiplication/division process in the next SMF because, as indicated in i) above, the CRC-4 bit positions in an SMF are initially set at 0 during the multiplication/division process. 2.3.3.5.3Decoding procedure i) A received SMF is acted upon by the multiplication/division pro- cess, referred to above in section 2.3.3.5.1 after having its CRC-4 bits extracted and replaced by zeros. ii) The remainder resulting from this division process is then stored and subsequently compared on a bit by bit basis with the CRC bits received in the next SMF. iii) If the remainder calculated in the decoder exactly corresponds to the CRC-4 bits received in the next SMF, it is assumed that the checked SMF is error free. 2.4 Basic frame structure at 8448 kbit/s 2.4.1 Frame length The number of bits per frame is 1056. They are numbered from 1 to 1056. The frame repetition rate is 8000Hz. 2.4.2 Frame alignment signal The frame alignment signal is:11100110 100000 and occupies the bit- positions 1 to 8 and 529 to 534. 2.4.3 Service digits Bit 535 is used to convey alarm indication (bit 535 at 1 state = alarm; bit 535 at 0 state = no alarm). Bit 536 is left free for national use and should be fixed at 1 on paths crossing the international border. The same applies to bits 9 - 40 in the case of channel-associated signalling. 3. Characteristics of frame structure carrying channels at various bit rates in 1544 kbit/s 3.1 Interface at 1544 kbit/s carrying 64 kbit/s channels 3.1.1 Frame structure 3.1.1.1 Number of bits per 64 kbit/s channel time slot Eight, numbered 1 to 8. 3.1.1.2 Number of 64 kbit/s channel time slots per frame Bits 2 to 193 in the basic frame carry 24 octet interleaved 64 kbit/s chan- nel time slots, numbered 1 to 24. 3.1.1.3 Allocation of F-bit Refer to section 2.1.3. 3.1.2 Use of 64 kbit/s channel time slots Each 64 kbit/s channel time slot can accommodate e.g., a PCM encoded voiceband signal conforming to G.711 or data information with a bit rate up to 64 kbit/s. 3.1.3 Signalling Two alternative methods as given in sections 3.1.3.1 and 3.1.3.2 are rec- ommended: 3.1.3.1 Common channel signalling One 64 kbit/s channel time slot is used to provide common channel sig- nalling at a rate of 64 kbit/s. In the case of the 12-frame multiframe method 2 above, the pattern of the S-bit may be arranged to carry com- mon channel signalling at a rate of 4 kbit/s or a sub-multiple of this rate. 3.1.3.2 Common associated signalling 3.1.3.2.1Allocation of signalling bits for 24-frame multiframe As can be seen in Table 1/G.704, there are four different signalling bits (A, B, C and D) in the multiframe. This channel associated signalling can provide four independent 333-bit/s signalling channels designated A, B, C and D, two independent 667-bit/s signalling channels designated A and B (see note) or one 1333-bit/s signalling channel. Note - When only four state signalling is required the AB signalling bits previously associated with frames 6 and 12 respectively should be mapped into ABCD signalling bits of frame 6, 12, 18 and 24 respectively as follows: A=A, B=B, C=A, D=B. In this case the ABCD signalling is the same as the AB signalling specified in section3.1.3.2.2 below. 3.1.3.2.2Allocation of signalling bits for 12-frame multiframe Based on agreement between the administrations involved, channel- associated signalling is provided for intra-regional circuits according to the following arrangement: A multiframe comprises 12 frames as shown in Table 5/G.704. The mul- tiframe alignment signal is carried on the S-bit as shown in the table. Frames 6 and 12 are designated as signalling frames. The eight bit in each channel time slot is used in every signalling frame to carry the sig- nalling associated with that channel. TABLE 5/G.704 Multiframe structure +ûûûûûû+ûûûûûûûûûûûû+ûûûûûûûûûûû+ûûûûûûûûûûûûûûûûûûûûûûûû +ûûûûûûûûûûûûû+ _ _ Frame _Multiframe _ Bit number(s) in each _ Signalling _ _Frame _ alignment _ alignment _ channel time slot _ channel _ _number_ signal _ signal +ûûûûûûûûûûûûû+ûûûûûûûûûû+ designa- tion _ _ _(see Note 1)_ (S bit) _For character_ For _ (see Note 2)_ _ _ _ _ signal _signalling_ _ +ûûûûûû+ûûûûûûûûûûûû+ûûûûûûûûûûû+ûûûûûûûûûûûûû+ûûûûûûûûûû +ûûûûûûûûûûûûû+ _ 1 _ 1 _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ 2 _ - _ 0 _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ 3 _ 0 _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ 4 _ - _ 0 _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ 5 _ 1 _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ 6 _ - _ 1 _ 1 - 7 _ 8 _ A _ _ _ _ _ _ _ _ _ 7 _ 0 _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ 8 _ - _ 1 _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ 9 _ 1 _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ 10 _ - _ 1 _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ 11 _ 0 _ - _ 1 - 8 _ - _ _ _ _ _ _ _ _ _ _ 12 _ - _ 0 _ 1 - 7 _ 8 _ B _ +ûûûûûû+ûûûûûûûûûûûû+ûûûûûûûûûûû+ûûûûûûûûûûûûû+ûûûûûûûûûû +ûûûûûûûûûûûûû+ Note 1 - When the S-bit is modified to signal the alarm indications to the remote end, the S-bit in frame 12 is changed from state 0 to 1. Note 2 - Channel associated signalling provides two independent 667-bit/ s signalling channels designated A and B or one 1333-bit/s signalling channel. 3.2 Interface at 1544 kbit/s carrying 32 kbit/s channels time slot (Note) Note - This interface provides for the carrying of 32 kbit/s information. The interface will be used between network nodes and will apply to pri- mary rate multiplexing equipment, digital cross-connect equipment, transcoder and other equipment relevant to the network nodes. Switching in this case is assumed to take place on a 64 kbit/s basis. 3.2.1 Frame structure 3.2.1.1 Number of bits per 32kbit/s channel time slot Four, number 1 to 4. 3.2.1.2 Number of 32 kbit/s channel time slot per frame Bits 2 to 193 in the basic frame can carry 4-bit interleaved forty- eight 32kbit/s channel time slots, numbered 1 to 48. 3.2.1.3 Allocation of F-bits Refer to section 2.1.3. 3.2.2 Use of 32 kbit/s channel time slot Each 32kbit/s channel time slot can accommodate an ADPCM encoded voiceband signal conforming to G.721 or data with a bit rate up to 32kbit/s. 3.2.3 384 kbit/s twelve channel time slot grouping 3.2.3.1 Structure of twelve channel time slot grouping The structure of the 11544kbit/s frame for 32kbit/s channel time slots shown in Table6/G.704 which is structured to provide four independent 384kbit/s twelve channel time slot groupings. These are numbered 1-4, and transmitted in numbered order starting with time slot grouping number1. The signalling grouping channels for time slot groupings 1-4, occupy time slots 12, 24, 36 and 48 respectively. Each time slot grouping can be independently configured for either situations requiring channel associ- ated signalling or situations with no signalling requirement (e.g. external common signalling). (See section3.2.3.1.1.) TABLE 6/G.704 32 kbit/s channel time slots frame structure for 1544 kbit/s interface Time slot grouping No. 1:123456789101112 (SGC) Time slot grouping No. 2:131415161718192021222324 (SGC) Time slot grouping No.3:252627282930313233343536 (SGC) Time slot grouping No. 4:373839404142434445464748 (SGC) Note 1 - Each time slot signifies 32 kbit/s channel. Note 2 - The signalling grouping channel (SGC) occupies the twelfth 32 kbit/s time slot of each time slot grouping. Note 3 - Definitions for time slot grouping and signalling grouping chan- nel are shown in section3.2.3. 3.2.3.1.1Use of a 384kbit/s time slot grouping Use of a 384kbit/s time slot grouping is categorized into two possible configurations: - when no signalling capabilities are required, a 384kbit/s time slot grouping can carry twelve 32kbit/s channel time slots; - when channel associated signalling capabilities are required, a 384kbit/s time slot grouping will consist of eleven 32kbit/s channel time slots and a 32kbit/s channel time slot defined as signalling grouping channel. 3.2.3.1.2Use of a signalling grouping channel A signalling grouping channel is used for the transmission of channel associated A-B-C-D signalling information, signalling grouping channel alarm information, the signalling grouping channel multiframe alignment signal, and CRC-6 error detection information between network nodes. 3.2.4 32 kbit/s signalling grouping channel multiframe structure 3.2.4.1 Number of bits per 32kbit/s signalling grouping channel time slot Four, numbers 1 to 4. 3.2.4.2 Bit allocation of 32kbit/s signalling grouping channel time slot Allocated to the last four bits of each time slot grouping. 3.2.4.3 Multiframe structure The signalling grouping channel multiframe structure consists of 24 con- secutive frames numbered from 1 to 24. Table7/G.704 shows the signal- ling grouping channel multiframe structure. 3.2.4.4 Signalling grouping channel multiframe alignment signal Bit 3 of the signal grouping channel, as shown in Table7, contains the signal grouping channel multiframe alignment signal used to associate the signalling bits in the signal grouping channel with the proper chan- nels of the associated time slot grouping. Note - The signal grouping channel multiframe alignment signal is inde- pendent of and different from the framing bit of the 1544kbit/s frame. 3.2.4.5 CRC-6 error detection information for the time slot grouping An optional 2kbit/s CRC-6 error detection code word may be transmit- ted in the bit position indicated by CRC-1 through CRC-6 in Table7/ G.704. The CRC-6 message block (CMB) is a sequence of 1152 serial bits that is coincident with a time slot grouping multiframe. By definition, CMBN begins at bit position 0 of time slot grouping multiframeN and ends at bit position 1151 of time slot grouping multiframe N. The check-bit sequence CRC-1 through CRC-6 transmitted in multiframe N+1 is the remainder after multiplication by X6, and then division (Modulo2) by the generator polynomial X6+X+1 of the polynomial corresponding to CMBN. The first check bit, CRC-1, is the most signif- icant bit of the remainder; the last check bit, CRC-6, is the least signifi- cant bit. The time slot grouping channel is included in this calculation with bit4 of the time slot grouping channel being set to 1. TABLE 7/G.704 32 kbit/s signalling grouping channel multiframe structure Note 1 - i = 1 for 12th 32 kbit/s channel time slot i = 12 for 24th 32 kbit/s channel time slot i = 25 for 36th 32 kbit/s channel time slot i = 37 for 48th 32 kbit/s channel time slot Note 2 - (Ai, Bi, Ci, Di): A-B-C-D signalling bits Mj: Signalling grouping channel alarm indication bits Sk: Spare bits Note 3 - The signalling grouping channel provides A-B-C-D signalling capability for 11channels within each time slot grouping. When not utilizing the option to transmit the CRC-6 error detection sig- nal, CRC-1 through CRC-6 shall be set to 1. 3.2.4.6 Signalling Two alternative methods as given in sections3.2.4.6.1 and 3.2.4.6.2 are recommended. 3.2.4.6.1Common channel signalling Refer to section 3.1.3.1. Two successive 32kbit/s channel time slots are used for 64kbit/s common channel signalling transmission. 3.2.4.6.2Channel associated signalling As indicated in Table7/G.704, bits 1 and 2 of the signalling grouping channel convey the channel associated signalling information for the channels of the associated time slot grouping. The signalling grouping channel can provide four independent 333bit/s signalling channels designated A-B-C-D, two independent 667bit/s sig- nalling channels designated A-B signalling, or one 1333bit/s signalling channel designated A. Where only A-B signalling is used, the A-B sig- nalling is repeated for the C-D positions respectively. Where only A sig- nalling is used, the A signalling is repeated for the B-C-D positions respectively. 3.2.4.7 Signalling grouping channel alarm indication signals As indicated in Table7/G.704, the signalling grouping channel contains four alarm indication bits, M1, M2, M3 and M4. M1 provides the capability to transmit through the interface a remote time slot grouping alarm indication of a failure in the opposite direction of transmission. M2 provides the capability to transmit through the interface an indication of a failure in tributary input signals to the network node. M3 provides the capability to transmit through the interface an indication of a failure in tributary output signals from the network node. M4 is set to one whenever M1 and/or M2 and/or M3 are set to one. 3.2.5 Signal grouping channel unused bits The bits marks S in Table7/G.704 are currently unused and set to 1. The definition and allocation of the S bits are for further study. 3.2.6 Loss and recovery of signalling channel multiframe alignment Loss of the signalling grouping channel multiframe alignment signal is declared when 2 out of 4 signalling grouping channel framing bits are in error. The rare occurrence of a single instantaneous slip of + or - 11 frames is undetected by the two-out-of-four algorithm. Signalling group- ing channel multiframe alignment shall be declared when the correct sequence of 24 valid signalling grouping channel framing bits are detected beginning with the first frame of the multiframe. 3.3 Interface at 1544 kbit/s carrying n x 64 kbit/s Electrical characteristics should follow RecommendationG.703. The time slot mapping to the 1544 kbit/s interface is for further study. 4. Characteristics of frame structure carrying channels at various bit rates in 6312 kbit/s interface 4.1 Interface at 6312 kbit/s carrying 64 kbit/s channels 4.1.1 Frame structure 4.1.1.1 Number of bits per 64 kbit/s channel time slot Eight, numbered 1 to 8. 4.1.1.2 Number of 64 kbit/s channel time slots per frame Bits 1 to 784 in the basic frame carry 98 octet interleaved 64 kbit/s chan- nel time slots, numbered 1 to 98. Five bits per frame (F-bits) are added at the end of the frame for the frame alignment signal and for other signals. 4.1.1.3 Allocation of the F-bits Refer to Table 3/G.704. 4.1.2. Use of 64 kbit/s channel time slots Each 64 kbit/s channel time slot can accommodate e.g., a PCM encoded voiceband signal conforming to RecommendationG.11 or data informa- tion with a bit rate up to 64 kbit/s. 64 kbit/s channel time slots 97, 98 may be used for signalling. 4.1.3 Signalling Two alternative methods as given in sections 4.1.3.1 and 4.1.3.2 are rec- ommended: 4.1.3.1 Common channel signalling Use of 64 kbit/s channel time slots 97 and 98 for common channel signal- ling is under study. 4.1.3.2 Channel associated signalling Based on agreement between the administrations involved, channel asso- ciated signalling is provided for intra-regional circuits according to the following arrangement: 4.1.3.2.1Allocation of signalling bit Sixteen signalling bits (bit positions 769 to 784) are designated as St1 to ST16. One STi-bit (i=1 to 16) accommodates signalling information cor- responding to six channel time slots i, 16+i, 32+i, 48+i, 64+i and 80+i in a manner described in section4.1.3.2.2 below. 4.1.3.2.2Signalling multiframe structure Each ST bit constitutes an independent signalling multiframe over eight frames as shown in Table 8/G.704. TABLE 8/G.704 Signalling multiframe structure +ûûûûûûûû+ûûûûûûûûûûûûûû+ûûûûû+ûûûûû+ûûûûû+ûûûûû+ûûûûû+ûû ûûû+ûûûûûûûûûûûûûû+ _Frame_ n _n+1_n+2_n+3_n+4_n+5_n+6_n+7 _ _number_ _ _ _ _ _ _ _ _ +ûûûûûûûû+ûûûûûûûûûûûûûû+ûûûûû+ûûûûû+ûûûûû+ûûûûû+ûûûûû+ûû ûûû+ûûûûûûûûûûûûûû+ _Use of_ Fs _ S1 _ S2 _ S3 _ S4 _ S5 _ S6 _ Sp _ _ST bit+ûûûûûûûûûûûûûû+ûûûûû+ûûûûû+ûûûûû+ûûûûû+ûûûûû+ûûûû û+ûûûûûûûûûûûûûû+ _ _ (See Note 1) _ (See Note 2) _(See Note 4)_ +ûûûûûûûû+ûûûûûûûûûûûûûû+ûûûûûûûûûûûûûûûûûûûûûûûûûûûûûûûûû ûû+ûûûûûûûûûûûûûû+ Note 1 - The Fs bit is either alternate 0, 1 or the following 48 bit digital pattern: A10101101100000110011010100111001111011010000101 For the 48 bit digital pattern, the "A" bit is usually fixed to state 1 and is reserved for optional use. The pattern is generated according to the fol- lowing primitive polynomial (refer to Recommendation X.50): X7+X4+1. Note 2 - Sj - bit (j=1 to 6) carries channel associated signalling or mainte- nance information. When the 48 bit pattern is adopted as Fs frame align- ment signal, each Sj - bit (j=1 to 6) can be multiframed, as follows: Sj1, Sj2, ûûûûûûûûûûûûûûûûû, Sj12 Sj1 bit carries the following 16 bit frame alignment pattern generated according to the same primitive polynomial as for the 48 bit pattern. A011101011011000. The "A" bit is usually fixed to 1 and is reserved for optional use. each Sji(i=2 to 12) bit carries channel associated signalling for sub-rate cir- cuits and/or maintenance information. Note 3 - ST bits (Fs, S1, ûûûûûûûûûûû,S6, and Sp) all at state 1 indicates Alarm Indication Signal (AIS) for six 64 kbit/s channels. Note 4 - The Sp bit is usually fixed to state 1. When backward AIS for six 64kbit/s channels is required to be sent, the SP bit is set to state 0. 4.2 Interfaces at 6312 kbit/s carrying other channels than 64 kbit/s For further study. 5. Characteristics of frame structure carrying channels at various bit rates in 2048 kbit/s interface 5.1 Interface at 2048 kbit/s carrying 64 kbit/s channels 5.1.1 Frame structure 5.1.1.1 Number of bits per 64 kbit/s channel time slot Eight, numbered 1 to 8. 5.1.1.2 Number of 64 kbit/s channel time slots per frame Bits 1 to 256 in the basic frame carry 32 octet interleaved time slots num- bered 0 to 31. 5.1.1.3 Allocation of the bits of 64 kbit/s channel time slot 0 See Table 4a/G.704, (section 2.3.2). 5.1.2 Use of other 64 kbit/s channel time slots Each of the 64 kbit/s channel time slots 1 to 15 and 17 to 31 can accom- modate e.g., a PCM encoded voiceband signal according to Recommen- dation G.711 or a 64 kbit/s digital signal. The 64 kbit/s channel time slot 16 may be used for signalling. If not needed for signalling, in some cases it may be used for a 64 kbit/s chan- nel, in the same way as time slots 1 to 15 and 17 to 31. 5.1.3 Signalling The use of 64 kbit/s channel time slot 16 is recommended for either com- mon channel or channel associated signalling as required. The detailed requirements for the organization of particular signalling systems will be included in the specifications for those signalling sys- tems. 5.1.3.1 Common channel signalling The 64 kbit/s channel time slot 16 may be used for common channel sig- nalling up to a rate of 64 kbit/s. The method of obtaining signal align- ment will form part of the particular common channel signalling specification. 5.1.3.2 Channel associated signalling This paragraph contains the recommended arrangement for the use of the 64kbit/s capability of channel time slot 16 for channel associated signal- ling. 5.1.3.2.1Multiframe structure A multiframe comprises 16 consecutive frames (whose structure is given in section 5.1.1 above) and these are numbered from 0 to 15. The multiframe alignment signal is 0000 and occupies digit time slots 1 to 4 of 64 kbit/s channel time slot 16 in frame 0. 5.1.3.2.2Allocation of 64 kbit/s channel time slot 16 When 64 kbit/s channel time slot 16 is used for channel associated signal- ling, the 64 kbit/s capacity is sub-multiplexed into lower-rate signalling channels using the multiframe alignment signal as a reference. Details of the bit allocation are given in Table 9/G.704. TABLE 9/G.704 Bit allocation of channel associated 64 kbit/s time slot 16 for channel associated signalling +ûûûûûûûûûûûûûû+ûûûûûûûûûûûûûû+ûûûûûûûûûûûûûû+ûûûûû+ûûûûû ûûûûûûûûûû+ _Time slot16_Time slot16_Time slot 16__Time slot 16_ _ of frame 0 _ of frame 1 _ of frame 2 _ --- _of frame 15_ +ûûûûûûûûûûûûûû+ûûûûûû+ûûûûûûû+ûûûûûû+ûûûûûûû+ûûûûû+ûûûûû ûû+ûûûûûûû+ _ 0000 xyxx _ abcd _ abcd _ abcd _ abcd _ --- _ abcd _ abcd _ _ _ _ _ _ _ _ _ _ _ _ ch. 1_ch. 16 _ ch. 2_ch. 17 _ _ch. 15 _ch. 30 _ +ûûûûûûûûûûûûûû+ûûûûûû+ûûûûûûû+ûûûûûû+ûûûûûûû+ûûûûû+ûûûûû ûû+ûûûûûûû+ Note 1 - Channel numbers refer to telephone channel numbers. 64/kbit/s channel time slots 1 to 15 and 17 to 31 are assigned to telephone channels numbered from 1 to 30. Note 2 - This bit allocation provides four 500-bit/s signalling channels designated a, b, c and d for each channel for telephone and other services. With this arrangement, the signalling distortion of each signalling chan- nel introduced by the PCM transmission system, will not exceed ▒2 ms. Note 3 - When bits b, c, or d are not used they should have the values: b=1 c=0 d=1 It is recommended that the combination 0000 of bits a, b, c and d should not be used for signalling purposes for channels 1-15. Note 4 - x=spare bit, to be set at state 1 if not used. y=bit used for alarm indication to the remote end. In undisturbed operation, 0; in an alarm condition, 1. 5.2 Interface at 2048 kbit/s carrying n x 64 kbit/s Electrical characteristics should follow Recommendation G.703 (see Note 4 of Preamble to G.703). For the accommodation of n x 64 kbit time slots in the 2048 kbit/s frame, two situations are envisaged. 5.2.1 One n x 64 kbit/s signal on the tributary side of a multiplex equip- ment Time slots of the 2048 kbit/s frame are filled as follows: TS 0 - according to º 2.3/G.704; TS 16 - reserved for the accommodation, if required, of a 64 kbit/s signalling channel. - If 2 _ n _ 15, TS 1 to TS n are filled with n x 64 kbit/s data (see Figure 1(a)/G.704); - If 15 < n _ 30, TS 1 to TS 15 and TS 17 to TS (n+1) are filled with n x 64 kbit/s data (see Figure 1(b)/G.704); - Remaining time slots are filled with all ones. FIGURE 1/G.704 5.2.2 One or more n x 64 kbit/s signal on the multiplexed signal side of a multiplexing equipment For any one n x 64 kbit/s signal, time slots of the 2048 kbit/s frame are filled as follows: TS 0 - according to º 2.3/G.704; TS 16 - reserved for the accommodation, if required, of a 64 kbit/s sig- nalling channel. TS (x) of the 2048 kbit/s frame is designated as the time slot into which the first time slot of the n x 64 kbit/s is accommodated. - If x _ 15 and x + (n-1) _ 15, or, if x _ 17 and x + (n-1) _ 31, then the filling of time slots is from TS (x) to TS (x+n-1) (see Figure 2(a) and 2(b)/G.704); - If x + (n-1) _ 16, then the filling of time slots is from TS (x) to TS 15 and TS 17 to TS (x+n) (see Figure 2(c)/G.704); Note - Once one n x 64 kbit/s signal has been accommodated into the multiplexed signal, care should be taken in the interpretation of the above rules to ensure that further such signals only use the time slots which remain spare. FIGURE 2/G.704 6. Characteristics of frame structure carrying channels at various bit bit rates in 8448 kbit/s interface 6.1 Interface at 8448 kbit/s carrying 64 kbit/s channels 6.1.1 Frame structure 6.1.1.1 Number of bits per 64 kbit/s channel time slot Eight, numbered from 1 to 8. 6.1.1.2 Number of 64 kbit/s channel time slots per frame Bits 1 to 1056 in the basic frame carry 132 octet interleaved 64kbit/s channel time slots, numbered from 0 to 131. 6.1.2 Use of 64 kbit/s channel time slots 6.1.2.1 64 kbit/s channel time slot assignment in case of channel-associ- ated signalling 6.1.2.1.164 kbit/s channel time slots 5 to 32, 34 to 65, 71 to 98 and 100 to 131 are assigned to 120 telephone channels numbered from 1 to 120. 6.1.2.1.264 kbit/s channel time slot 0 and the first 6 bits in 64 kbit/s channel time slot 66 are assigned to framing: the remaining 2 bits in 64kbit/s channel time slot 66 are devoted to services. 6.1.2.1.364 kbit/s channel time slots 67 to 70 are assigned to channel- associated signalling as covered in section 6.1.3.2 below. 6.1.2.1.464 kbit/s channel time slots 1 to 4, 33 are left free for national use. 6.1.2.2 64 kbit/s channel time slot assignment in case of common channel signalling 6.1.2.2.164 kbit/s channel time slots 2 to 32, 34 to 65, 67 to 98 and 100 to 131 are available for 127 telephone, signalling or other service chan- nels. By bilateral agreement between the administrations involved, 64 kbit/s channel time slot 1 may either be used to provide another telephone or service channel or left free for service purposes within a digital exchange. The 64 kbit/s channels corresponding to 64 kbit/s channel time slot 1 to 32, 34 to 65 (etc. as above) are numbered 0 to 127. 6.1.2.2.264 kbit/s channel time slot 0 and the first 6 bits in channel time slot 66 are assigned to framing, the remaining 2 bits in 64 kbit/s channel time slot 66 are assigned to service. 6.1.2.2.364 kbit/s channel time slots 67 to 70 are in descending order of priority available for common channel signalling as covered in section6.1.3.1 below. 6.1.2.2.464 kbit/s channel slot 33 is left free for national use. 6.1.3 Description of the CRC procedure in 64kbit/s channel time slot 99 In order to provide an end-to-end quality monitoring of the 8Mbit/s link, a CRC-6 procedure is used and the six bits C1 to C6 computed at the source location are inserted in bit positions 1 to 6 of the time slot 99 (Figure3/G.704). In addition, bit 7 of this time slot, denoted E, is used to transmit an indi- cation about the received signal in the opposite direction, whether the most recent CRC block has been received with errors or not. The CRC-6 bits C1 to C6 are computed for each frame. The CRC-6 block size is then 132 octets, i.e. 1056bits, and the computation is made 8000 times per second. _C1_C2_C3_C4_C5_C6_E_S_ +ûûûû+ûûûû+ûûûû+ûûûû+ûûûû+ûûûû+ûûû+ûûû+ bit 18 FIGURE 3/G.704 Time slot 99 6.1.3.1Multiplication - division process A given C1 - C6 word located in frame N is the remainder after multipli- cation by X6 and then division (modulo 2) by the generator polynomial X6+X+1 of the polynomial representation of frame (N-1). Note - When representing the contents of a frame as a polynomial, the first bit in the frame should be taken as being the most significant bit. Similarly C1 is defined to be the most significant bit of the remainder and C6 the least significant bit of the remainder. 6.1.3.2Encoding procedure 6.1.3.2.1The CRC bit positions are initially set at 0 i.e.: C1 = C2 = C3 = C4 = C5 = C6 = 0 6.1.3.2.2The frame is then acted upon by the multiplication/division process referred to above in 6.1.3.1. 6.1.3.2.3The remainder resulting from the multiplication/division pro- cess is stored ready for insertion into the respective CRC locations at the next frame. Note - These CRC bits do not affect the computation of the CRC bits in the next frame since the corresponding locations are set at zero before the computation. 6.1.3.3Decoding procedure 6.1.3.3.1A received frame is acted upon by the multiplication/division process, referred to above in section 6.1.3.1 after having its CRC bits extracted and replaced by zeros. 6.1.3.3.2The remainder resulting from this multiplication/division pro- cess is then stored and subsequently compared on a bit by bit basis with the CRC received in the next frame. 6.1.3.3.3If the decoder calculated remainder exactly corresponds to the CRC bits sent from the encoder, it is assumed that the checked frame is error free. 6.1.3.4Action on bit E Bit E of frame N is set at 1 in the transmitting direction is bits C1-6 detected in the most recent frame in the opposite direction have been found in error (at least one bit in error). In the opposite case it is set at zero. 6.1.4 Signalling The use of channel time slots 67 to 70 is recommended for either com- mon channel or channel-associated signalling as required. The detailed requirements for the organization of particular signalling systems will be included in the specifications for those signalling systems. 6.1.4.1 Common channel signalling 64 kbit/s channel time slots 67 to 70 may be used for common channel signalling in a descending order of priority up to a rate of 64 kbit/s. The method of obtaining signal alignment will form part of the particular common channel signalling specification. 6.1.4.2 Channel associated signalling The Recommendation arrangement for the use of the 64 kbit/s capacity each 64 kbit/s channel time slot 67 to 70 for channel-associated signal- ling is as follows: 6.1.4.2.1 Multiframe structure A multiframe for each 64 kbit/s bit-stream comprises 16 consecutive frames (whose structure is given in section 6.1.1 above) and these are numbered from 0 to 15. The multiframe alignment signal is 0000 and occupies digit time slots 1 to 4 of channel time slots 67 to 70 in frame 0. 6.1.4.2.2Allocation of 64 kbit/s channel time slots 67 to 70 When 64 kbit/s channel time slots 67 to 70 are used for channel associ- ated signalling the 64 kbit/s capacity of each of the four 64 kbit/s channel time slots is sub-multiplexed into lower rate signalling channels using the multiframe alignment signal as a reference. Details of the bit allocation are given in Table 10/G.704. TABLE 10/G.704 Bit allocation of 64 kbit/s channel time slots 67 to 70 +ûûûûûûûûûûûûûûûûûûûûû+ûûûûûûûûûûûûû+ûûûûûûûûûûûûû+ûûûûûûû ûûûûûû+ûûûûûûûûûûûûû+ _64 kbit/s_ _ _ _ _ _ Channel _ 67 _ 68 _ 69 _ 70 _ _ time slot _ _ _ _ _ _ _ _ _ _ _ _Frame _ _ _ _ _ +ûûûûûûûûûûûûûûûûûûûûû+ûûûûûûûûûûûûû+ûûûûûûûûûûûûû+ûûûûûûû ûûûûûû+ûûûûûûûûûûûûû+ _ 0 _ 0000xyxx _ 0000xyxx _ 0000xyxx _ 0000xyxx _ +ûûûûûûûûûûûûûûûûûûûûû+ûûûûûû+ûûûûûû+ûûûûûû+ûûûûûû+ûûûûûû +ûûûûûû+ûûûûûû+ûûûûûû+ _ _abcd_abcd_abcd_abcd_abcd_abcd_abcd_abcd_ _1_________ _ _ ch.1 _ ch.16_ ch.31_ ch.46_ ch.61_ ch.76_ ch.91_ch.106_ +ûûûûûûûûûûûûûûûûûûûûû+ûûûûûû+ûûûûûû+ûûûûûû+ûûûûûû+ûûûûûû +ûûûûûû+ûûûûûû+ûûûûûû+ _ : _ : _ : _ : _ : _ : _ : _ : _ : _ +ûûûûûûûûûûûûûûûûûûûûû+ûûûûûû+ûûûûûû+ûûûûûû+ûûûûûû+ûûûûûû +ûûûûûû+ûûûûûû+ûûûûûû+ _ _ abcd _ abcd _ abcd _ abcd _ abcd _ abcd _ abcd _ abcd _ _15_________ _ _ ch.15_ ch.30_ ch.45_ ch.60_ ch.75_ ch.90_ch.105_ch.120_ +ûûûûûûûûûûûûûûûûûûûûû+ûûûûûû+ûûûûûû+ûûûûûû+ûûûûûû+ûûûûûû +ûûûûûû+ûûûûûû+ûûûûûû+ Note 1 - Channel numbers refer to telephone channel numbers. Refer to section6.1.2.1.1 for the assignment of 64 kbit/s channel time slots to the telephone channels. Note 2 - This bit allocation provides four 500-bit/s signalling channels designated a, b, c and d for each channel for telephone and other services. With this arrangement, the signalling distortion of each signalling chan- nel introduced by the PCM transmission system, will not exceed -+2 ms. Note 3 - When bits b, c or d are not used they should have the value: b=1 c=0 d=1 It is recommended that the combination 0000 of bits a, c, c and d should not be used for signalling purposes for channels 1-15, 31-45, 61-75 and 91-125. Note 4 - x = spare bit, to be set at state 1 if not used. y = bit used for alarm indication to the remote end. In undisturbed operation, 0; in an alarm condition, 1. 6.2 Interface at 8448 kbit/s carrying other channels than 64 kbit/s For further study. Annex (to Recommendation G.704) Examples of CRC Implementations using sift registers a) CRC-6 procedure for interface at 1544 kbit/s (Reference:section2.1.3.1.2) Input: CMB N with F bits set to 1Generator polynomial: x6+x+1 Insert Figure here T1802270-86 At I, the CMB is fed serially (i.e. bit by bit) into the circuit, starting with bit number 1 of the multiframe (see Table 1/G.704). When the last bit of the CMB (i.e., bit number 4632 within the multiframe 4632) has been fed into the shift register, the CRC bits e1 to e6 are available at the outputs 1 to 6. (Output 1 provides the most significant bit, e1, and output 6 the least significant bit, e6.) Bits e1 to e6 are transmitted in the next CMB (c.f. Table 1/G.704). Note - The outputs (1 to 6) of the shift register stages are reset to 0 after each CMB. b) CRC-5 procedure for interface at 6312 kbit/s (Reference:section2.2.3.2) Input:CMBNGenerator polynomial:x5 + x4 + x2 + 1 Insert Figure here T18002280-86 At I, the CMB is fed serially (i.e., bit by bit) into the circuit, starting with bit number 1 of frame number 1 (see Table 3/G.704). When the last bit of the CMB (i.e., bit number 784 of frame number 4) has been fed into the shift register, the CRC bits e1 to e5 are available at the outputs 1 to 5. (Output 1 provides the most significant bit, e1 and output 5 the least sig- nificant bit e5.) Bits e1 to e5 are transmitted in the corresponding multiframe (see Table 3/G.703). Note - The outputs (1 to 5) of the shift register stages are reset to 0 after each CMB. c) CRC-4 procedure for interface at 2048 kbit/s (Reference:section2.3.3.5) Input: SMF(N) with C1=C2=C3=C4 set to 0Generator polynomial: x4+x+1 Insert Figure here T18002290-86 At I, the SMF is fed serially (i.e., bit by bit) into the circuit, starting with bit C1=0 (see Table 4b/G.704). When the last bit of the SMF (i.e., bit number 256 of frame number 7, respectively of frame number 15) has been fed into the shift register, the CRC bits B1 to C4 are available at the outputs 1 to 4. (Output 1 provides the most significant bit, C1, and output 4 the least significant bit, C4.) Bits C1 to C4 are transmitted in the next SMF, i.e., SMF(N+1). Note - The outputs (1 to 4) of the shift-register stages are reset to 0 after each SMF.