InfoMagic Standards 1993 July/Disc.iso/ccitt/1988/troff/8_1_05.tro

Text File | 1991-12-22 | 80.6 KB | 3,173 lines

.rs
.\" Troff code generated by TPS Convert from ITU Original Files
.\"                 Not Copyright (~c) 1991
.\"
.\" Assumes tbl, eqn, MS macros, and lots of luck.
.TA 1c 2c 3c 4c 5c 6c 7c 8c
.ds CH
.ds CF
.EQ
delim @@
.EN
.nr LL 40.5P
.nr ll 40.5P
.nr HM 3P
.nr FM 6P
.nr PO 4P
.nr PD 9p
.po 4P

.rs
\v'|.5i'
.sp 2P
.LP
\fBRecommendation\ V.32\fR
.RT
.sp 2P
.ce 1000
\fBA\ FAMILY\ OF\fR \
\fB2\(hyWIRE,\ DUPLEX\ MODEMS\ OPERATING\ AT\fR
.EF '%    Fascicle\ VIII.1\ \(em\ Rec.\ V.32''
.OF '''Fascicle\ VIII.1\ \(em\ Rec.\ V.32    %'
.ce 0
.ce 1000
\fBDATA\ SIGNALLING\ RATES\ OF\ UP\ TO\ 9600\ bit/s\fR \ \fBFOR\ USE\ ON\
THE\fR
.ce 0
.ce 1000
\fBGENERAL\ SWITCHED\ TELEPHONE\ NETWORK\ AND\ ON\fR \
\fBLEASED\fR
.ce 0
.sp 1P
.ce 1000
\fBTELEPHONE\(hyTYPE\ CIRCUITS\fR
.ce 0
.sp 1P
.ce 1000
\fI(Malaga\(hyTorremolinos, 1984, amended at Melbourne, 1988)\fR
.sp 9p
.RT
.ce 0
.sp 1P
.LP
\fB1\fR     \fBIntroduction\fR
.sp 1P
.RT
.PP
This family of modems is intended for use on connections on general switched
telephone networks (GSTNs) (see Note\ 1) and on
point\(hyto\(hypoint
leased telephone\(hytype circuits
. The principal characteristics of the modems are as follows:
.RT
.LP
    a)
    Duplex mode of operation on GSTN and 2\(hywire point\(hyto\(hypoint
.LP
leased circuits (see Note\ 2).
.LP
    b)
    Channel separation by echo cancellation techniques.
.LP
    c)
    Quadrature amplitude modulation
for each channel
with
synchronous line transmission
at 2400\ bauds.
.LP
    d)
     Any combination of the following data signalling rates may be implemented
in the modems:
.LP
    9600 bit/s synchronous,
.LP
    4800 bit/s synchronous,
.LP
    2400 bit/s synchronous (for further study).
.LP
    e)
    At 9600 bit/s, two alternative modulation schemes, one using
16 carrier states and one using
trellis coding
with 32
carrier states, are provided for in this Recommendation.
However, modems providing the 9600\ bit/s data signalling rate
shall be capable of interworking using the 16\(hystate
alternative.
.LP
    f
)
    Exchange of rate sequences during start\(hyup to
establish the data rate, coding and any other special
facilities.
.LP
    g)
    Optional provision of an asynchronous mode of operation
in accordance with Recommendation\ V.14.
.PP
\fINote\ 1\fR \ \(em\ On international GSTN connections that utilize circuits
that are in accord with Recommen
dation\ G.235 (16\(hychannel terminal
equipments),
it may be necessary to employ a greater degree of equalization within the
modem than would be required for use on most national GSTN connections.
.PP
\fINote\ 2\fR \ \(em\ The transmit and receive rates in each modem shall
be the same. The possibility of asymmetric working remains for further
study.
.RT
.sp 2P
.LP
\fB2\fR     \fBLine signals\fR
.sp 1P
.RT
.sp 1P
.LP
2.1
    \fICarrier frequency\fR
.sp 9p
.RT
.PP
The carrier frequency is to be 1800\ \(+-\ 1 Hz. No separate pilot tones
are to be provided. The receiver must be able to operate with received
frequency offsets of up to\ \(+-\|7\ Hz.
.RT
.sp 1P
.LP
2.2
    \fITransmitted spectrum\fR
.sp 9p
.RT
.PP
The transmitted power level must conform to Recommendation\ V.2.
With continuous binary ones applied to the input of the scrambler, the
transmitted energy density at 600\ Hz and 3000\ Hz should be attenuated
4.5\ \(+-\ 2.5\ dB with respect to the maximum energy density between 600\
Hz and
3000\ Hz.
.RT
.LP
.sp 1P
.LP
2.3
    \fIModulation rate\fR
.sp 9p
.RT
.PP
The modulation rate shall be 2400 bauds \(+-\ 0.01%.
.RT
.sp 2P
.LP
2.4
    \fICoding\fR
.sp 1P
.RT
.sp 1P
.LP
2.4.1
    \fISignal element coding for 9600 bit/s\fR
.sp 9p
.RT
.PP
Two alternatives are defined:
.bp
.RT
.sp 1P
.LP
2.4.1.1
    \fINonredundant coding\fR
.sp 9p
.RT
.PP
The scrambled data stream to be transmitted is divided into groups of 4
consecutive data bits. The first two bits in time Q1\dn\uand Q2\dn\uin
each group, where the subscript n designates the sequence number of the
group, are differentially encoded into Y1\dn\uand Y2\dn\uaccording to Table\
1/V.32.
Bits Y1\dn\u, Y2\dn\u, Q3\dn\uand Q4\dn\uare then mapped into the coordinates
of the signal state to be transmitted according to the signal space diagram
shown in Figure 1/V.32 and as listed in Table\ 3/V.32.
.RT
.LP
.sp 1P
.LP
2.4.1.2
    \fITrellis coding\fR
.sp 9p
.RT
.PP
The scrambled data stream to be transmitted is divided into groups of 4
consecutive data bits. As shown in Figure\ 2/V.32, the first two bits in
time Q1\dn\uand Q2\dn\uin each group, where the subscript n designates the
sequence number of the group, are first differentially encoded into Y1\dn\uand
Y2\dn\uaccording to Table\ 2/V.32. The two differentially encoded bits
Y1\dn\uand Y2\dn\uare used as input to a systematic
convolutional encoder
which generates a redundant bit Y0\dn\u. This redundant bit and the 4
information\(hycarrying bits Y1\dn\u, Y2\dn\u, Q3\dn\uand Q4\dn\uare then
mapped
into the coordinates of the signal element to be transmitted according
to the signal space diagram shown in Figure\ 3/V.32 and as listed in
Table\ 3/V.32.
.RT
.sp 1P
.LP
2.4.2
    \fISignal element coding for 4800 bit/s\fR
.sp 9p
.RT
.PP
The scrambled data stream to be transmitted is divided into groups of 2
consecutive data bits. These bits, denoted Q1\dn\uand Q2\dn\u, where Q1\dn\uis
the first in time, and the subscript n designates the sequence number of
the group, are differentially encoded into Y1\dn\uand Y2\dn\uaccording
to
Table\ 1/V.32. Figure\ 1/V.32 shows the subset\ A, B, C and\ D of signal states
used for 4800\ bit/s transmission.
.RT
.LP
.sp 1P
.LP
2.4.3
    \fISignal element coding for 2400 bit/s\fR
.sp 9p
.RT
.PP
(For further study.)
.RT
.sp 2P
.LP
\fB3\fR     \fBInterchange circuits\fR
.sp 1P
.RT
.sp 1P
.LP
3.1
    \fIList of interchange circuits\fR
.sp 9p
.RT
.PP
These are listed in Table 4/V.32 below.
.RT
.sp 1P
.LP
3.2
    \fITransmit data\fR
.sp 9p
.RT
.PP
The modems shall accept synchronous data from the DTE on
circuit\ 103 under control of circuit\ 113 or\ 114.
.RT
.sp 1P
.LP
3.3
    \fIReceive data\fR
.sp 9p
.RT
.PP
The modems shall pass synchronous data to the DTE on circuit\ 104
under the control of circuit\ 115.
.RT
.LP
.sp 1P
.LP
3.4
    \fITiming arrangements\fR
.sp 9p
.RT
.PP
Clocks shall be included in the modems to provide the DTE with
transmitter signal element timing on circuit\ 114 and receiver signal element
timing on circuit\ 115. The transmitter timing may originate in the DTE
and be transferred to the modem via circuit\ 113. In some applications
it may be
necessary to slave the transmitter timing to the receiver timing inside the
modem.
.RT
.sp 1P
.LP
3.5
    \fIData rate control\fR
.sp 9p
.RT
.PP
Data rate selection may be by switch (or similar means) or
alternatively by circuit\ 111. In cases where three different data signalling
rates are implemented in a modem, a manual selector may be provided which
determines the two data signalling rates selected by circuit\ 111.
.PP
The ON condition of circuit\ 111 selects the higher data signalling
rate and the OFF condition of circuit\ 111 selects the lower data signalling
rate.
.RT
.sp 1P
.LP
3.6
    \fICircuit 106\fR
.sp 9p
.RT
.PP
After the start\(hyup and retrain sequences, circuit 106 must follow the
state of circuit 105 within 2\ ms.
.bp
.RT
.ce
\fBH.T. [T1.32]\fR
.ce
TABLE\ 1/V.32
.ce
\fBDifferential quadrant coding for 4800 bit/s\fR
.ce
\fBand for nonredundant coding at 9600 bit/s\fR
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(18p) sw(18p) | cw(30p) sw(30p) | cw(48p) | cw(18p) sw(18p) | cw(48p) , c | c | c | c ^  | | c | c | ^ .
Inputs    Previous outputs    Phase quadrant change    Outputs    Signal state  for 4800 bit/s
Q1 n    Q2 n    Y1 n \(em 1    Y2 n \(em 1    Y1 n    Y2 n
_
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
0    0    0    0    +\ 90\(de    0    1    B
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
0    0    0    1        1    1    C
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
0    0    1    0        0    0    A
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
0    0    1    1        1    0    D
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
0    1    0    0    \ \ \ 0\(de    0    0    A
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
0    1    0    1        0    1    B
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
0    1    1    0        1    0    D
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
0    1    1    1        1    1    C
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
1    0    0    0    +180\(de    1    1    C
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
1    0    0    1        1    0    D
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
1    0    1    0        0    1    B
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
1    0    1    1        0    0    A
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
1    1    0    0    +270\(de    1    0    D
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
1    1    0    1        0    0    A
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
1    1    1    0        1    1    C
.T&
cw(18p) | cw(18p) | cw(30p) | cw(30p) | cw(48p) | cw(18p) | cw(18p) | cw(48p) .
1    1    1    1        0    1    B
_
.TE
.nr PS 9
.RT
.ad r
\fBTABLEAU 1/V.32 [T1.32], p. 1\fR
.sp 1P
.RT
.ad b
.RT
.LP
.rs
.sp 23P
.ad r
\fBFIGURE 1/V.32, p. 2\fR
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.LP
.rs
.sp 29P
.ad r
\fBFIGURE 2/V.32, p. 3\fR
.ad b
.RT
.ce
\fBH.T. [T2.32]\fR
.ce

.ce
TABLE\ 2/V.32
.ce
\fBDifferential encoding for use with trellis\fR
.ce
\fBcoded alternative at 9600 bit/s\fR
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(48p) | cw(84p) | cw(48p) .
Inputs    Previous outputs    Outputs
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
Q1 n    Q2 n    Y1 n \(em 1    Y2 n \(em 1    Y1 n    Y2 n
_
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    0    0    0    0    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    0    0    1    0    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    0    1    0    1    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    0    1    1    1    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    1    0    0    0    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    1    0    1    0    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    1    1    0    1    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    1    1    1    1    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    0    0    0    1    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    0    0    1    1    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    0    1    0    0    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    0    1    1    0    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    1    0    0    1    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    1    0    1    1    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    1    1    0    0    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    1    1    1    0    1
_
.TE
.nr PS 9
.RT
.ad r
\fBTABLEAU 2/V.32 [T2.32], p. 4\fR
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.ce
\fBH.T. [T3.32]\fR
.ce

.ce
TABLE\ 3/V.32
.ce
\fBThe two alternative signal\(hystate mappings for 9600 bit/s\fR
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(90p) | cw(42p) | cw(48p) .
T{
Coded inputs
(see Table 1/V.32 or Table 2/V.32 with
Figure\ 2/V.32)
T}    Nonredundant coding    Trellis coding
_
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
(Y0)    Y1    Y2    Q3    Q4    Re    Im    Re    Im
_
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
0    0    0    0    0    \(em1    \(em1    \(em4    \ 1
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    0    0    1    \(em3    \(em1    \ 0    \(em3
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    0    1    0    \(em1    \(em3    \ 0    \ 1
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    0    1    1    \(em3    \(em3    \ 4    \ 1
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    1    0    0    \ 1    \(em1    \ 4    \(em1
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    1    0    1    \ 1    \(em3    \ 0    \ 3
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    1    1    0    \ 3    \(em1    \ 0    \(em1
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    1    1    1    \ 3    \(em3    \(em4    \(em1
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    0    0    0    \(em1    \ 1    \(em2    \ 3
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    0    0    1    \(em1    \ 3    \(em2    \(em1
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    0    1    0    \(em3    \ 1    \ 2    \ 3
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    0    1    1    \(em3    \ 3    \ 2    \(em1
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    1    0    0    \ 1    \ 1    \ 2    \(em3
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    1    0    1    \ 3    \ 1    \ 2    \ 1
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    1    1    0    \ 1    \ 3    \(em2    \(em3
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    1    1    1    \ 3    \ 3    \(em2    \ 1
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
1    0    0    0    0            \(em3    \(em2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    0    0    1            \ 1    \(em2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    0    1    0            \(em3    \ 2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    0    1    1            \ 1    \ 2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    1    0    0            \ 3    \ 2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    1    0    1            \(em1    \ 2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    1    1    0            \ 3    \(em2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    0    1    1    1            \(em1    \(em2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    0    0    0            \ 1    \ 4
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    0    0    1            \(em3    \ 0
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    0    1    0            \ 1    \ 0
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    0    1    1            \ 1    \(em4
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    1    0    0            \(em1    \(em4
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    1    0    1            \ 3    \ 0
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    1    1    0            \(em1    \ 0
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(24p) | cw(24p) | cw(24p) .
    1    1    1    1            \(em1    \ 4
_
.TE
.nr PS 9
.RT
.ad r
\fBTABLEAU 3/V.32 [T3.32], p. 5\fR
.sp 1P
.RT
.ad b
.RT
.LP
.rs
.sp 05P
.ad r
BLANC
.ad b
.RT
.LP
.bp
.LP
.rs
.sp 47P
.ad r
\fBFIGURE 3/V.32, p. 6\fR
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.ce
\fBH.T. [T4.32]\fR
.ce
TABLE\ 4/V.32
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(36p) sw(108p) | cw(36p) , c | c | ^ .
T{
Interchange circuit (see Note 1)
T}    Notes
No.    Description
.T&
cw(36p) | lw(108p) | lw(36p) .
102    T{
Signal ground or common return
T}
_
.T&
cw(36p) | lw(108p) | lw(36p) .
103    Transmitted data
.T&
cw(36p) | lw(108p) | lw(36p) .
104    Received data
.T&
cw(36p) | lw(108p) | lw(36p) .
105    Request to send
.T&
cw(36p) | lw(108p) | lw(36p) .
106    Ready for sending
_
.T&
cw(36p) | lw(108p) | lw(36p) .
107    Data set ready
.T&
cw(36p) | lw(108p) | cw(36p) .
108/1 or    Connect data set to line    2
.T&
cw(36p) | lw(108p) | cw(36p) .
108/2    Data terminal ready    2
.T&
cw(36p) | lw(108p) | cw(36p) .
109    T{
Data channel received line signal detector
T}
_
.T&
cw(36p) | lw(108p) | cw(36p) .
111    T{
Data signalling rate selector (DTE source)
T}    3
.T&
cw(36p) | lw(108p) | cw(36p) .
112    T{
Data signalling rate selector (DCE source)
T}    3
.T&
cw(36p) | lw(108p) | cw(36p) .
113    T{
Transmitter signal element timing
(DTE source)
T}    5
.T&
cw(36p) | lw(108p) | cw(36p) .
114    T{
Transmitter signal element timing
(DCE source)
T}    6
.T&
cw(36p) | lw(108p) | cw(36p) .
115    T{
Receiver signal element timing
(DCE source)
T}    6
.T&
cw(36p) | lw(108p) | cw(36p) .
125    Calling indicator    4
.T&
cw(36p) | lw(108p) | cw(36p) .
140    Loopback/maintenance test
.T&
cw(36p) | lw(108p) | cw(36p) .
141    Local loopback
.T&
cw(36p) | lw(108p) | cw(36p) .
142    Test indicator
.TE
.LP
\fINote\ 1\fR
\ \(em\ All interchange circuits which are provided shall comply
with the functional and operational requirements of Recommendation\ V.24.
All interchange circuits shall be properly terminated in the data terminal
equipment and in the data circuit\(hyterminating equipment in accordance with
the appropriate Recommendation for electrical characteristics
(see \(sc\ 3.8).
.LP
\fINote\ 2\fR
\ \(em\ This circuit shall be capable of operation as circuit 108/1 or
circuit\ 108/2 depending on its use. Operation of circuits\ 107 and\ 108/1
shall be in accordance with \(sc\ 4.4 of Recommendation\ V.24.
.LP
\fINote\ 3\fR
\ \(em\ This circuit is not essential when only one data signalling rate
is implemented in the modem.
.LP
\fINote\ 4\fR
\ \(em\ This circuit is for use with the general switched telephone
network only.
.LP
\fINote\ 5\fR
\ \(em\ When the modem is not operating in a synchronous mode at the
interface, any signals on this circuit shall be disregarded. Many DTEs
operating in an asynchronous mode do not have a generator connected to this
circuit.
.LP
\fINote\ 6\fR
\ \(em\ When the modem is not operating in a synchronous mode at the
interface, this circuit shall be clamped to the OFF condition. Many DTEs
operating in an asynchronous mode do not terminate this circuit.
.LP
T}
_
.TE
.nr PS 9
.RT
.ad r
\fBTableau 4/V.32 [T4.32] + Remarques, p. 7\fR
.sp 1P
.RT
.ad b
.RT
.LP
.rs
.sp 04P
.ad r
BLANC
.ad b
.RT
.LP
.bp
.sp 1P
.LP
3.7
    \fICircuit 109\fR
.sp 9p
.RT
.PP
OFF to ON and ON to OFF transitions of circuit 109 should occur
solely in accordance with the operating sequences defined in \(sc\ 5. Thresholds
and response times are inapplicable because a line signal detector cannot be
expected to distinguish wanted received signals from unwanted talker
echoes.
.RT
.sp 2P
.LP
3.8
    \fIElectrical characteristics of interchange circuits\fR
.sp 1P
.RT
.LP
.PP
3.8.1
Use of electrical characteristics conforming to
Recommendation\ V.28 is recommended together with the connector and pin
assignment plan specified by ISO\ 2110.
.sp 9p
.RT
.PP
\fINote\fR \ \(em\ Manufacturers may wish to note that the long\(hyterm
objective is to replace electrical characteristics specified in
Recommendation\ V.28, and that Study Group\ XVII has agreed that the work
shall proceed to develop a more efficient, all\(hybalanced, interface for
the V\(hySeries application which minimizes the number of interchange circuits.
.sp 1P
.LP
3.9
    \fIFault condition on interchange circuits\fR
.sp 9p
.RT
.PP
See \(sc\ 7 of Recommendation V.28 for association of the receiver
failure detection
types.
.RT
.PP
3.9.1
The DTE should interpret a fault condition on circuit\ 107 as an OFF condition
using failure detection type\ 1.
.sp 9p
.RT
.PP
3.9.2
The DCE should interpret a fault condition on circuits 105 and\ 108 as
an OFF condition using failure detection type\ 1.
.PP
3.9.3
All other circuits not referred to above may use failure detection types\
0 or\ 1.
.LP
.sp 2P
.LP
\fB4\fR     \fBScrambler and descrambler\fR
.sp 1P
.RT
.PP
A self\(hysychronizing scrambler/descrambler shall be included in the modem.
Each transmission direction uses a different scrambler. The method of
allocating the scramblers/descramblers is described in \(sc\ 4.1. According
to the direction of transmission, the generating polynomial is:
.RT
.LP
    Call mode modem generating polynomial:
(GPC)\ =\ 1\ +\ \fIx\fR \uD\dlF261\u1\d\u8\d\ +\ \fIx\fR \uD\dlF261\u2\d\u3\d,
or
.LP
    Answer mode modem generating polynomial:
(GPA)\ =\ 1\ +\ \fIx\fR \uD\dlF261\u5\d\ +\ \fIx\fR \uD\dlF261\u2\d\u3\d
.PP
At the transmitter, the scrambler shall effectively divide the
message data sequence by the generating polynomial. The coefficients of the
quotients of this division, taken in descending order, form the data sequence
which shall appear at the output of the scrambler. At the receiver the
received data sequence shall be multiplied by the scrambler generating
polynomial to
recover the message sequence.
.LP
.sp 2P
.LP
4.1
    \fIScrambler/descrambler allocation\fR
.sp 1P
.RT
.sp 1P
.LP
4.1.1
    \fIGeneral switched telephone network (GSTN)\fR
.sp 9p
.RT
.PP
On the general switched telephone network, the modem at the calling data
station (call mode) shall use the scrambler with the GPC
generating
polynomial
and the descrambler with the GPA generating polynomial. The
modem at the answering data station (answer mode) shall use the scrambler
with the GPA generating polynomial and the descrambler with the GPC generating
polynomial. In some situations, however, such as when calls are established
on the GSTN by operators, bilateral agreement on call mode/answer mode
allocation will be necessary.
.RT
.sp 1P
.LP
4.1.2
    \fIPoint\(hyto\(hypoint leased circuits\fR
.sp 9p
.RT
.PP
Scrambler/descrambler allocation and call mode and answer mode
designation on point\(hyto\(hypoint leased circuits will be by bilateral
agreement
between Administrations or users.
.bp
.RT
.sp 2P
.LP
\fB5\fR     \fBOperating procedures\fR
.sp 1P
.RT
.sp 1P
.LP
5.1
    \fIRecommendation V.25 automatic answering sequence\fR
.sp 9p
.RT
.PP
The Recommendation V.25 automatic answering sequence shall be
.PP
transmitted from the answer mode modem on international GSTN connections.
The transmission of the sequence may be omitted on point\(hyto\(hypoint
leased circuits or on national connections on the GSTN where permitted
by Administrations. In this event, the answer mode modem shall initiate
transmission as in the
retrain
procedure specified in \(sc\ 5.5.
.RT
.sp 1P
.LP
5.2
    \fIReceiver\fR
\fIconditioning signal\fR
.sp 9p
.RT
.PP
The receiver
conditioning
signal shall be used in the
start\(hyup and retrain procedures defined in \(sc\(sc\ 5.4 and\ 5.5 below.
The signal
consists of three segments:
.RT
.PP
5.2.1
Segment 1, denoted by S in Figures\ 4/V.32 and 5/V.32,
consists of alternations between states\ A and\ B as shown in Figure\ 1/V.32,
for a duration of 256 symbol intervals.
.sp 9p
.RT
.PP
5.2.2
Segment 2, denoted by
S
in Figures\ 4/V.32
and 5/V.32,
consists of alternations between states\ C and\ D as shown in Figure\ 1/V.32,
for a duration of 16 symbol intervals.
.sp 9p
.RT
.PP
The transition from segment 1 to segment 2 provides a well\(hydefined event
in the signal that may be used for generating a time reference in the
receiver.
.LP
.rs
.sp 32P
.ad r
\fBFIGURE 4/V.32, p. 8\fR
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.LP
.rs
.sp 47P
.ad r
\fBFIGURE 5/V.32, p. 9\fR
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.PP
5.2.3
Segment 3, denoted by TRN in Figures\ 4/V.32 and 5/V.32, is a
sequence
derived by scrambling binary ones at a data rate of 4800\ bit/s with the
scrambler defined in \(sc\ 4. During the transmission of this segment, the
differential quadrant encoding shall be disabled. The initial state of the
scrambler shall be all zeros, and a binary one applied to the input for the
duration of segment\ 3. Successive dibits are encoded onto transmitted signal
states.
.sp 9p
.RT
.PP
The first 256 transmitted signal states are determined from the
state of the first bit occurring (in time) in each dibit. When this bit is
ZERO, signal state\ A is transmitted; when this bit is ONE, signal state\ C is
transmitted. Depending on whether the modem is in call or answer mode, the
scrambler output patterns and corresponding signal states will then begin as
below, where the bits and the signal states are shown in time sequence from
left to right.
.PP
Call mode modem:
.RT
.LP
    GPC:
    11\ 11\ 11\ 11\ 11\ 11\ 11\ 11\ 11\ 00\ 00\ 01\ 11\ 11\ 11
.LP
C
C
C
C
C
C
C
C
C
A
A
A
C
C
C
.PP
Answer mode modem:
.LP
    GPA:
    11\ 11\ 10\ 00\ 00\ 11\ 11\ 10\ 00\ 00\ 11\ 10\ 01\ 11\ 11
C
C
C
A
A
C
C
C
A
A
C
C
A
C
C
.PP
Immediately after 256 such symbols, successive scrambled
dibits
are encoded onto transmitted signal states in accordance with
Table\ 5/V.32 directly without differential encoding for the remainder of
segment\ 3. The duration of segment\ 3 shall be at least 1280 and not exceed
8192
.FS
The maximum duration of 8192 symbol intervals is for further
study.
.FE
symbol intervals.
.PP
Segment 3 is intended for training the
adaptive equaliser
in   the receiving modem and the
echo canceller
in the transmitting
modem.
.RT
.LP
.ce
\fBH.T. [T5.32]\fR
.ce
TABLE\ 5/V.32
.ce
\fBEncoding for TRN segment after the first 256 symbols\fR
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(60p) | cw(60p) .
Dibit    Signal state
_
.T&
cw(60p) | cw(60p) .
00    A
.T&
cw(60p) | cw(60p) .
01    B
.T&
cw(60p) | cw(60p) .
11    C
.T&
cw(60p) | cw(60p) .
10    D
.TE
.LP
\fINote\fR
\ \(em\ Signal states A, B, C and D are shown in Figure 1/V.32.
.nr PS 9
.RT
.ad r
\fBTABLEAU 5/V.32 [T5.32], p. 10\fR
.sp 1P
.RT
.ad b
.RT
.LP
.sp 2
.sp 1P
.LP
5.3
    \fIRate signal\fR
.sp 9p
.RT
.PP
The rate signal consists of a whole number of repeated 16\(hybit
binary sequences, as defined in
Table\ 6/V.32, scrambled and transmitted at 4800\ bit/s with dibits differentially
encoded as in Table\ 1/V.32. The
differential encoder shall be initialized using the final symbol of the
transmitted TRN segment.
.PP
The first two bits and each successive dibit of the rate sequence
shall be encoded to form the transmitted signal states.
.PP
The first transmitted octet, B0\(hyB7, is fully defined in Table\ 6/V.32
and shall be interpreted by all Recommendation\ V.32 modems; the second
octet, B8\(hyB15, includes some codes defined in the table, some to be
defined later and others to be left undefined for use by manufacturers.
.RT
.LP
.sp 1
.bp
.ce
\fBH.T. [T6.32]\fR
.ce
TABLE\ 6/V.32
.ce
\fBCoding of the 16\(hybit rate sequence\fR
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(15p) | cw(9p) | cw(9p) | cw(9p) | cw(15p) | cw(9p) | cw(9p) | cw(9p) | cw(15p) | cw(9p) | cw(9p) | cw(9p) | cw(15p) | cw(9p) | cw(9p) | cw(9p) | lw(60p) .
B0 B 0    B1 B 0    B2 B 0    B3 B 0    B4 \(em    B5 \(em    B6 \(em    B7 B 1    B8 \(em    B9 \(em    10 \(em    11 \ 1    12 \(em    13 \(em    14 \(em    15 \ 1    T{
B0\ B1\ B2\ B3\ B4\ etc.
B
0\
B
0\
B
0\
B
0\ \(em
T}
_
.T&
lw(60p) | lw(168p) .
B0\(hy3, B7, 11, 15    T{
For synchronizing on a received rate signal
T}
.T&
lw(60p) | lw(168p) .
B4    T{
1\ denotes ability to receive data at 2400 bit/s
T}
.T&
lw(60p) | lw(168p) .
B5    T{
1\ denotes ability to receive data at 4800 bit/s
T}
.T&
lw(60p) | lw(168p) .
B6    T{
1\ denotes ability to receive data at 9600 bit/s
T}
.T&
lw(60p) | lw(168p) .
B4\(hy6    T{
0 0 0\ calls for a GSTN cleardown
T}
.T&
lw(60p) | lw(168p) .
B8    T{
1\ denotes availability of trellis coding/decoding at the highest data
rate indicated in B4\(hy6
T}
.T&
lw(60p) | lw(168p) .
B9\(hy14    T{
0 0 1 0 0 0\ denotes absence of special operational
modes
T}
.TE
.LP

\fINote\fR
\ \(em\ The remaining codes may be allocated within Recommendation V.32
in the future.
.nr PS 9
.RT
.ad r
\fBTABLE 6/V.32 [T6.32], p.\fR
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
5.3.1
    \fIDetecting a rate signal\fR
.sp 9p
.RT
.PP
The minimum requirement for detection is the receipt of two
consecutive identical 16\(hybit sequences each with bits B0\(hy3, B7, 11
and\ 15
conforming to Table\ 6/V.32.
.RT
.LP
.sp 1P
.LP
5.3.2
    \fIEnding the rate signal\fR
.sp 9p
.RT
.PP
In order to mark the end of transmission of any rate signal other than
R1 (Figure\ 4/V.32), the modem shall first complete the transmission of
the current 16\(hybit rate sequence, and then transmit one 16\(hybit sequence\
E, coded as shown in Table\ 7/V.32.
.RT
.ce
\fBH.T. [T7.32]\fR
.ce
TABLE\ 7/V.32
.ce
\fBCoding of signal E\fR
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
B0 B 1    B1 B 1    B2 B 1    B3 B 1    B4 \(em    B5 \(em    B6 \(em    B7 B 1    B8 \(em    B9 \(em    10 \(em    11 \ 1    12 \(em    13 \(em    14 \(em    15 \ 1
_
.T&
lw(24p) | lw(168p) .
B4\(hy14    T{
As in Table 6/V.32, except that the only data rate and
coding to be indicated shall relate
to the transmission of
scrambled binary ones immediately following
signal\ E
T}
_
.TE
.nr PS 9
.RT
.ad r
\fBTABLE 7/V.32 [T7.32], p.\fR
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
5.4
    \fIStart\(hyup procedure\fR
.sp 9p
.RT
.PP
The procedure for achieving synchronism between the calling modem
.PP
and the answering modem on international GSTN connections is shown in
Figure\ 4/V.32. The procedure includes the estimating of
round\(hytrip
delay
from each modem, the
training of echo cancellers
and
receivers initially with half\(hyduplex transmissions, and the exchanging
of rate signals for automatic bit\(hyrate and mode selection.
.bp
.RT
.sp 1P
.LP
5.4.1
    \fICall mode modem\fR
.sp 9p
.RT
.PP
After receiving the answer tone for a period of at least 1\ s
as specified in Recommendation\ V.25, the modem shall be connected to line
(see Note\ 1 below) and shall condition the scrambler and descrambler in
accordance with \(sc\ 4.1.
.PP
The modem shall repetitively transmit carrier state A as shown in
Figure\ 1/V.32.
.PP
The modem shall be conditioned to detect (see Note 2 below) one of two
incoming tones at frequencies 600\ \(+-\ 7\ Hz and 3000\ \(+-\ 7\ Hz, and
subsequently to detect a phase reversal in that tone.
.PP
On detection of one such phase reversal, the modem shall be
conditioned to detect a second phase reversal in the same tone, start a
.PP
counter/timer and change to repetitively transmitting state\ C as shown in
Figure\ 1/V.32. The time delay between the reception of this phase reversal
at the line terminals and the transmitted AA to CC transition appearing
at the
line terminals shall be 64\ \(+-\ 2\ symbol periods.
.PP
On detection of a second phase reversal in the same incoming tone, the
modem shall stop the counter/timer and cease transmitting.
.PP
When the modem detects an incoming S sequence (see \(sc\ 5.2), it shall
proceed to train its receiver, and then seek to detect at least two consecutive
identical 16\(hybit rate sequences as defined in Table\ 6/V.32.
.PP
On detection of the rate signal (R1), the modem shall transmit an
S\ sequence for a period NT already estimated by the counter/timer.
.PP
After this period has expired (see Note\ 3 below), the modem shall
transmit the receiver conditioning signal as defined in \(sc\ 5.2, starting
with an S\ sequence for 256 symbol intervals.
.PP
Transmission of the TRN segment of the receiver conditioning signal
may be extended in order to ensure a satisfactory level of echo cancellation
(see Note\ 4 below).
.PP
After the TRN segment, the modem shall apply an ON condition to
circuit\ 107 and transmit a rate signal (R2) in accordance with \(sc\ 5.3 to
indicate the currently available data rates and whether trellis coding
and/or other special operational modes are available. R2 shall exclude
rates and
operational modes not appearing in the previously received rate signal\ R1.
It is recommended that R2 should also take
account of the likely receiver performance with the particular GSTN connection.
If it appears that satisfactory performance cannot be attained at any of
the
available data rates, then R2 should be used to call for a GSTN cleardown in
accordance with Table\ 6/V.32.
.PP
Transmission of R2 shall continue until an incoming rate signal R3 is detected.
The modem shall then, after completing its current 16\(hybit rate
sequence, transmit a single 16\(hybit sequence\ E in accordance with \(sc\
5.3.2
indicating the data rate, coding and any special operational modes called
for in R3. If, however, R3 is calling for a GSTN cleardown in accordance
with
Table\ 6/V.32, then the call modem shall disconnect from line and effect a
cleardown.
.PP
The modem shall then transmit continuous scrambled binary ones at
.PP
the data rate and with the coding called for in R3, and apply the appropriate
condition to circuit\ 112. If trellis coding according to \(sc\ 2.4.1.2
is to be
used, the initial states of the delay elements of the convolution encoder
shown in Figure\ 2/V.32 should be set to zero.
.PP
On detecting an incoming 16\(hybit E sequence as defined in \(sc\ 5.3.2,
the modem shall condition itself to receive data at the rate and with the
coding
indicated by the incoming E sequence. After a delay of 128\ symbol intervals,
it shall apply an ON condition to circuit\ 109, and unclamp circuit\ 104.
.PP
The modem shall then enable circuit 106 to respond to the condition of
circuit\ 105 and be ready to transmit data.
.RT
.sp 1P
.LP
5.4.2
    \fIAnswer mode modem\fR
.sp 9p
.RT
.PP
On connection to line, the modem shall condition the scrambler and descrambler
in accordance with \(sc\ 4.1, and transmit the Recommendation\ V.25
answer sequence. Means, defined in Recommendation\ V.25, of disabling network
echo cancellers and/or truncating the answer tone may be employed.
.PP
After the Recommendation\ V.25 answer sequence, the modem shall
transmit alternate carrier states\ A and\ C as shown in Figure\ 1/V.32.
.PP
After alternate states\ A and C have been transmitted for an even
number of symbol intervals greater than or equal to 128 \fIand\fR an incoming
tone has been detected at 1800\ \(+-\ 7\ Hz for 64\ symbol periods (see
Note\ 5 below), the modem shall be conditioned to detect a phase reversal
in the incoming tone,
start a counter/timer, and change to transmitting alternate carrier states\ C
and\ A for an even number of symbol intervals.
.bp
.PP
On detecting a phase reversal in the incoming tone, the modem shall
stop the counter/timer and, after transmitting a state\ A, revert to
transmitting alternate states\ A and\ C. The time delay between the reception
of this phase reversal at the line terminals and the transmitted CA to
AC
transition appearing at the line terminals shall be 64\ \(+-\ 2\ symbol
periods.
.PP
When an amplitude drop is detected in the incoming tone, the modem
shall cease transmitting for a period of 16\ symbol intervals and then (see
Note\ 3) transmit the receiver conditioning signal as defined in \(sc\ 5.2.
.PP
Transmission of the TRN segment of the receiver conditioning signal
may be extended in order to ensure a satisfactory level of echo cancellation
(see Note\ 4).
.PP
After the TRN segment, the modem shall transmit a rate signal (R1)
in accordance with \(sc\ 5.3 to indicate the data rates, coding and any special
operational modes currently available in the answer modem and associated DTE.
.PP
On detection of an incoming S sequence, the modem shall cease
transmitting.
.PP
The modem shall wait for a period MT
already estimated by the counter/timer and then, if an incoming S\ sequence
persists, or when an S\ sequence reappears (see Note\ 3), the modem shall
proceed to train its receiver.
.PP
After training its receiver, the modem shall seek to detect at least two
consecutive identical incoming 16\(hybit rate sequences as defined in \(sc\
5.3.
.PP
On detection of a rate signal (R2), the modem shall apply an ON
condition to circuit\ 107 and transmit a second receiver conditioning signal
as defined in \(sc\ 5.2.
.PP
After the TRN segment, the modem shall transmit a second rate signal (R3)
in order to indicate the data rate, coding and any special operational
.PP
modes to be used by both modems. The data rate and operational modes selected
by\ R3 shall be within those indicated by\ R2. It is
recommended that R3 should also take account of the likely performance
of the answer modem receiver with the particular GSTN connection established.
If R2 is calling for a GSTN cleardown (see Table\ 6/V.32) and/or if it
appears that
satisfactory performance cannot be attained by the answer modem at any
of the available data rates, then R3 should call for a GSTN cleardown,
in accordance with Table\ 6/V.32.
.PP
When the modem detects an incoming 16\(hybit E sequence as defined in
\(sc\ 5.3.2, it shall condition itself to receive data at the rate and with the
coding indicated by the E\ sequence.
.PP
The modem shall complete the current 16\(hybit rate sequence and then
transmit a single 16\(hybit E sequence indicating the data rate and coding
to be used in the subsequent transmission of scrambled binary ones. If
trellis coding according to \(sc\ 2.4.1.2 is to be used, then the initial
states of the delay
elements of the convolution encoder shown in Figure\ 3/V.32 should be set
to\ zero.
.PP
The modem shall transmit scrambled binary ones for 128 symbol
.PP
intervals, then enable circuit\ 106 to respond to the condition of circuit\
105 and be ready to transmit data.
.PP
The modem shall also apply an ON condition to circuit\ 109 and unclamp
circuit\ 104.
.PP
\fINote\ 1\fR \ \(em\ Once an incoming tone is detected at 600\ \(+-\ 7\ Hz or
3000\ \(+-\ 7\ Hz, the calling modem should proceed with the start\(hyup
sequence even if no 2100\ Hz tone has been detected.
.PP
\fINote\ 2\fR \ \(em\ In some cases, the incoming tones may be preceded by a
special pattern which may last up to\ 294\ ms (see Appendix\ I).
.PP
\fINote\ 3\fR \ \(em\ The
TRN segment
in the receiver conditioning signal is suitable for training the echo canceller
in the transmitting modem.
Alternatively, it is acceptable to precede the receiver conditioning signal
by a sequence which can be used specifically for training the echo canceller,
but which need not be defined in detail in the Recommendation. The echo
cancellation sequence (if used) must maintain energy transmitted to line to
hold network echo control devices disabled (as required). In order to avoid
confusion with Segments\ 1 or\ 2 of the receiver conditioning signal defined
in \(sc\ 5.2, the echo cancellation sequence shall produce a transmitted
signal such that the sum of its power in the three 200\ Hz bands centred
at 600\ Hz,
1800\ Hz and 3000\ Hz is at least 1\ dB less than its power in the remaining
bandwidth. This applies for the relative power averaged over any 6\ ms time
.PP
interval. The duration of this signal must not exceed\ 8192
.FS
The maximum
duration of 8192 symbol intervals is for further study.
.FE
symbol intervals.
.PP
\fINote\ 4\fR \ \(em\ Manufacturers are cautioned that a period of 650\ ms is
needed for training any network echo cancellers conforming to
Recommendation\ G.165, that may be encountered on GSTN connections.
.bp
.PP
\fINote\ 5\fR \ \(em\ The answering modem may disconnect from the line if the
1800\ \(+-\ 7\ Hz tone is not detected following transmission of the segment
AC.
However, to assure compatibility with manual originating data stations, it
shall not disconnect for at least 3 seconds after the segment AC has been
transmitted.
.RT
.sp 1P
.LP
5.5
    \fIRetrain procedure\fR
.sp 9p
.RT
.PP
A retrain may be initiated during data transmission if either modem incorporates
a means of detecting unsatisfactory signal reception.
Figure\ 5a/V.32 shows a retrain event initiated by the calling modem and
.PP
Figure\ 5b/V.32 shows a retrain event initiated by the answering modem. The
procedure is as follows:
.RT
.sp 1P
.LP
5.5.1
    \fICall mode modem\fR
.sp 9p
.RT
.PP
Following detection of unsatisfactory signal reception or detection of
one of two tones at frequencies 600\ \(+-\ 7\ Hz and 3000\ \(+-\ 7\ Hz
for more than
128\ symbol intervals, the modem shall turn OFF circuit\ 106, clamp circuit\
104 to binary one and repetitively transmit carrier state\ A as shown in
Figure\ 1/V.32. It shall then proceed in accordance with \(sc\ 5.4.1 beginning
with the third paragraph (see Note in \(sc\ 5.5.2).
.RT
.sp 1P
.LP
5.5.2
    \fIAnswer mode modem\fR
.sp 9p
.RT
.PP
Following detection of unsatisfactory signal reception or detection of
a tone of frequency\ 1800\ \(+-\ 7\ Hz for more than 128 symbol intervals,
the
modem shall turn OFF circuit\ 106, clamp circuit\ 104 to binary one and
transmit alternate carrier states\ A and\ C for an even number of symbol
intervals not
less than\ 128. It shall then proceed in accordance with \(sc\ 5.4.2 beginning
with the third paragraph (see Note).
.PP
\fINote\fR \ \(em\ During a retrain, circuit 107 should remain ON.
.PP
(The need for a shorter duplex retrain procedure to provide for rapid training
of the modem receivers is for further study.)
.RT
.sp 1P
.LP
5.5.3
    \fIOperation of circuit 109 during retrain procedure\fR
.sp 9p
.RT
.PP
Circuit 109 shall be maintained in the ON condition except that the OFF
condition may optionally be applied if transmission of the AA segment in
the Call modem or of the first AC segment in the Answer modem continues
for a period exceeding 45\ seconds. If the retrain procedure is subsequently
completed, the ON condition shall be re\(hyapplied to circuit\ 109 at the
time that circuit\ 104 is unclamped.
.RT
.sp 2P
.LP
\fB6\fR     \fBTesting facilities\fR
.sp 1P
.RT
.PP
Test loops
2 and 3 as defined in Recommendation V.54 should be provided. Provision
for test loop\ 2 shall be as specified for point\(hyto\(hypoint circuits.
.RT
.sp 2P
.LP
\fB7\fR \fBAsynchronous to synchronous conversion protocol\fR \fB\(em Modes\fR
\fBof operation\fR
.sp 1P
.RT
.PP
The modem can be configured for the following modes of operation
(modes\ 2 and\ 4 are optional):
.RT
.LP
    Mode 1\ \ 9600 bit/s \(+-0.01% synchronous
.LP
    Mode 2\ \ 9600 bit/s start\(hystop 8, 9, 10 or 11 bits per character
.LP
    Mode 3\ \ 4800 bit/s \(+-0.01% synchronous
.LP
    Mode 4\ \ 4800 bit/s start\(hystop 8, 9, 10 or 11 bits per
character
.sp 2P
.LP
7.1
    \fITransmitter\fR
.sp 1P
.RT
.PP
7.1.1
In the synchronous modes of operation, the modem shall accept
synchronous data from the DTE on circuit\ 103 under control of circuit\ 113 or
circuit\ 114. The data shall then be scrambled in accordance with \(sc\
4 and then passed to the modulator for encoding in accordance with \(sc\
2.4.
.bp
.sp 9p
.RT
.PP
7.1.2
In the start\(hystop modes, the modem shall accept a data stream of
start\(hystop characters from the DTE at a nominal rate of 9600 or 4800\
bit/s per second. The start\(hystop data to be transmitted shall be converted
in conformity with Recommendation\ V.14 to a synchronous data stream suitable
for transmission in accordance with \(sc\ 7.1.1.
.sp 1P
.LP
7.2
    \fIReceiver\fR
.sp 9p
.RT
.PP
Demodulated data shall be decoded in accordance with \(sc\ 2.4, then
descrambled in accordance with \(sc\ 4 and then passed to the converter in
conformity with Recommendation\ V.14 for regaining the data stream of start\(hystop
characters.
.PP
The intracharacter signalling rate provided to the DTE over
circuit\ 104 shall be in the ranges given in Table\ 8/V.32 when operating
in the basic, or in the extended signalling rate ranges, respectively.
.RT
.ce
\fBH.T. [T8.32]\fR
.ce
TABLE\ 8/V.32
.ce
\fBIntracharacter signalling rate range\fR
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(60p) | cw(60p) sw(60p) , ^  | c | c.
Data rate    Signalling rate range
    Basic    Extended
_
.T&
cw(60p) | cw(60p) | cw(60p) .
9600 bit/s    9600 to 9696 bit/s    9600 to 9821 bit/s
.T&
cw(60p) | cw(60p) | cw(60p) .
4800 bit/s    4800 to 4848 bit/s    4800 to 4910 bit/s
_
.TE
.nr PS 9
.RT
.ad r
\fBTable 8/V.32 [T8.32], p.\fR
.sp 1P
.RT
.ad b
.RT
.LP
.sp 2
.ce 1000
APPENDIX\ I
.ce 0
.ce 1000
(to Recommendation V.32)
.sp 9p
.RT
.ce 0
.ce 1000
\fBInterworking procedure for echo cancelling modems\fR
.sp 1P
.RT
.ce 0
.LP
\fIConsidering\fR
.sp 1P
.RT
.PP
\(em
that the V.26\|\fIter\fR modem at 2400 bit/s
and the V.32 modems at 9600\ bit/s and 4800\ bit/s are based on
the same technique, referred to as echo cancellation;
.PP
\(em
that the 1800 Hz carrier frequency is the same for
the two modems;
.PP
\(em
that there may be a need for a modem, referred to as
multimode, able to interwork with V.26\|\fIter\fR and
V.32 modems;
.PP
\(em
that the determination of round\(hytrip delay may be
useful in some cases,
.LP
the handshaking operating sequence defined in the following paragraphs is
provided for the information of manufacturers.
.sp 1P
.LP
I.1
    \fIInterworking of echo cancelling modems\fR
.sp 9p
.RT
.PP
The V.32 modems at 9600 bit/s and 4800 bit/s and the V.26\|\fIter\fR
modems at 2400\ bit/s could interwork with a dedicated multimode modem
implementing both V.32 and\ V.26\|\fIter\fR capabilities, as illustrated in
Table\ I\(hy1/V.32.
.bp
.RT
.LP
.rs
.sp 21P
.ad r
\fBTableau I\(hy1/V.32 comme figure, p. 14\fR
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
I.1.1
    \fIOperation of the calling multimode modem\fR
.sp 9p
.RT
.PP
The modem will recognize:
.RT
.LP
    \(em
    A V.26\|\fIter\fR modem by detecting the 1200 baud
synchronization signals followed by a rate pattern and then
will proceed as defined in V.26\|\fIter\fR (see
Figure\ I\(hy1/V.32).
.LP
    \(em
    V.32 modems by the detection of one of two
incoming tones at frequencies 600\ \(+-\ 7\ Hz and 3000\ \(+-\ 7\ Hz (see
.LP
Figure I\(hy2/V.32). It will then proceed as defined in \(sc\ 5.4.1.
.LP
    \(em
    A multimode modem by the detection of a special rate pattern
assigned to the multimode modem. It will transmit, as shown in
Figure\ I\(hy3/V.32, repetitively carrier state\ A or the
synchronizing signals followed by the rate pattern, according to
the selected mode of operation: V.32 or
V.26\|\fIter\fR respectively.
.LP
.sp 1P
.LP
I.1.2
    \fIOperation of the answering multimode modem\fR
.sp 9p
.RT
.PP
After the V.25 sequence, the modem will transmit the
1200\ baud synchronizing signals followed by its special rate pattern,
and then alternate carrier states\ A and\ C as defined in Recommendation\
V.32.
.PP
It will recognize during the transmission of these alternate carrier states\
A and\ C:
.RT
.LP
    \(em
    a V.26\|\fIter\fR modem by the detection of the
1200 baud synchronizing signals followed by a rate pattern.
It will stop transmitting alternate carrier states\ A and\ C and
proceed according to Recommendation\ V.26\|\fIter\fR (see
Figure\ I\(hy4/V.32);
.LP
    \(em
    V.32 modems by recognizing a tone at
1800\ \(+-\ 7\ Hz and will then proceed as defined in
Recommendation\ V.32 (see Figure\ I\(hy5/V.32).
.PP
The case of multimode modems on both answering and calling sides has been
considered in \(sc\ I.1.1.
.bp
.LP
.rs
.sp 47P
.ad r
\fBFIGURES I\(hy1/V.32 \*`a I\(hy5/V.32, p.\fR
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.sp 2P
.LP
\fBRecommendation\ V.33\fR
.RT
.sp 2P
.ce 1000
\fB14\|400\ BITS\ PER\ SECOND\ MODEM\ STANDARDIZED\ FOR\ USE\ ON\fR
.EF '%    Fascicle\ VIII.1\ \(em\ Rec.\ V.33''
.OF '''Fascicle\ VIII.1\ \(em\ Rec.\ V.33    %'
.ce 0
.sp 1P
.ce 1000
\fBPOINT\(hyTO\(hyPOINT\ 4\(hyWIRE\ LEASED\ TELEPHONE\(hyTYPE\ CIRCUITS\fR
.ce 0
.sp 1P
.ce 1000
\fI(Melbourne, 1988)\fR
.sp 9p
.RT
.ce 0
.sp 1P
.LP
\fB1\fR     \fBIntroduction\fR
.sp 1P
.RT
.PP
This modem is intended to be used primarily on special quality
leased circuits, e.g.\ Recommen
dation\ M.1020\ [1] or M.1025\ [2] circuits but   this
does not preclude the use of this modem over circuits of lower quality
at the discretion of the administration concerned (see Notes\ 1 and\ 2).
.PP
On leased circuits, considering that there exist and will come into
being many modems with features designed to meet the requirements of the
administrations and users, this Recommendation in no way restricts the
use of any other modems.
.PP
The principal characteristics of this modem are as follows:
.RT
.LP
    a)
    fallback rate of 12\|000 bits per second;
.LP
    b)
    capable of operating in a duplex mode with continuous
carrier;
.LP
    c)
    combined amplitude and phase modulation with synchronous
mode of operation;
.LP
    d)
    inclusion of an eight state trellis coded modulation;
.LP
\fR
    e)
    optional inclusion of a multiplexer for combining data
rates of 12\|000, 9600, 7200, 4800 and 2400\ bits per second (see Note\ 3).
.PP
\fINote\ 1\fR \ \(em\ The principal use of this recommended modem is on
4\(hywire leased circuits. Other applications, such as stand\(hyby operation
on the switched telephone network, half duplex or multipoint operation
are for further study. Circuits should be of the special quality type,
e.g.\ M.1020\ [1] or
M.1025\ [2].  However, administrations and users may wish to note that modems
conforming to this Recommendation, even assuming proper implementations,
will not necessarily operate satisfactorily on all circuits conforming
to M.1020 and M.1025; particularly where noise is at or near the specified
limiting
magnitude.
.PP
\fINote\ 2\fR \ \(em\ Attention should be given to the selection of appropriate
equalization techniques in the modem implementation, if acceptable performance
on circuits conforming to Recommendation\ M.1025 is desired.
.PP
\fINote\ 3\fR \ \(em\ When the multiplexer option is installed, provisions in
section\ 10 may supersede provisions given in other sections.
.RT
.sp 2P
.LP
\fB2\fR     \fBLine signals\fR
.sp 1P
.RT
.PP
2.1
The carrier frequency is to be 1800 \(+-\|1 Hz. The power levels
used will conform to Recommendation\ V.2.
.sp 9p
.RT
.sp 2P
.LP
2.2
    \fISignal space coding\fR
.sp 1P
.RT
.PP
2.2.1
At 14\|400 bits per second, the scrambled data stream to be
transmitted is divided into groups of six consecutive data bits. As shown in
Figure\ 1/V.33, the first two bits in time\ Q1\dn\uand Q2\dn\uin each group,
are first differentially encoded into Y1 and Y2 according to Table\ 1A/V.33.
The two differentially encoded bits Y1\dn\uand Y2\dn\uare used as input
to a systematic convolutional encoder which generates a redundant bit Y0\dn\u.
This redundant
bit and the six information\(hycarrying bits Y1\dn\u, Y2\dn\u, Q3\dn\u,
Q4\dn\u,
Q5\dn\uand Q6\dn\uare then mapped into the coordinates of the signal element
to be transmitted according to the signal space diagram shown in
Figure\ 2/V.33.
.sp 9p
.RT
.PP
2.2.2
At the fallback rate of 12\|000 bit/s, the scrambled data stream to be
transmitted is divided into groups of five consecutive data bits. The
trellis coding scheme shown in Figure\ 1/V.33, is used with the modification
that first, the line designated by Q6\dn\uis removed and second, the signal
element mapping is now as shown in Figure\ 3/V.33.
.PP
2.2.3
Table 1BB/FV.33 describes the differential encoding used for the
4800\ bit/s rate signal in segment\ 3 of synchronizing signals (\(sc\ 8.3).
.bp
.ce
\fBH.T. [T1.33]\fR
.ce
TABLE\ 1A/V.33
.ce
\fBDifferential encoding for use with trellis coding\fR
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(48p) | cw(84p) | cw(48p) .
Inputs    Previous outputs    Outputs
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
Q1 n    Q2 n    Y1 n \(em 1    Y2 n \(em 2    Y1 n    Y2 n
_
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    0    0    0    0    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    0    0    1    0    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    0    1    0    1    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    0    1    1    1    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    1    0    0    0    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    1    0    1    0    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    1    1    0    1    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
0    1    1    1    1    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    0    0    0    1    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    0    0    1    1    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    0    1    0    0    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    0    1    1    0    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    1    0    0    1    1
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    1    0    1    1    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    1    1    0    0    0
.T&
cw(24p) | cw(24p) | cw(42p) | cw(42p) | cw(24p) | cw(24p) .
1    1    1    1    0    1
_
.TE
.nr PS 9
.RT
.ad r
\fBTableau 1A/V.33 [T1.33], p. 16\fR
.sp 1P
.RT
.ad b
.RT
.ce
\fBH.T. [T2.33]\fR
.ce
TABLE\ 1B/V.33
.ce
\fBDifferential quadrant coding for 4800 bit/s rate signal\fR
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(18p) sw(18p) | cw(18p) sw(18p) | cw(42p) | cw(18p) sw(18p) | cw(42p) | cw(18p) sw(18p) , c | c | c | c ^  | | c | c ^  | | c | c.
Inputs      Previous outputs      Phase quadrant    Outputs      Signal element for 4800 bit/s    Coordinates
Q1 n    Q2 n    Y1 \dn\(em1 \u    Y2 \dn\(em1 \u    Y1 n    Y2 n    Re    Im
_
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
0    0    0    0    \ +90\uo\d    0    1    D    \(em2    +6
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
0    0    0    1        1    1    A    \(em6    \(em2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
0    0    1    0        0    0    C    +6    +2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
0    0    1    1        1    0    B    +2    \(em6
_
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
0    1    0    0    \ \ \ 0\uo\d    0    0    C    +6    +2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
0    1    0    1        0    1    D    \(em2    +6
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
0    1    1    0        1    0    B    +2    \(em6
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
0    1    1    1        1    1    A    \(em6    \(em2
_
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
1    0    0    0    +180\uo\d    1    1    A    \(em6    \(em2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
1    0    0    1        1    0    B    +2    \(em6
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
1    0    1    0        0    1    D    \(em2    +6
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
1    0    1    1        0    0    C    +6    +2
_
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
1    1    0    0    +270\uo\d    1    0    B    +2    \(em6
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
1    1    0    1        0    0    C    +6    +2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
1    1    1    0        1    1    A    \(em6    \(em2
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) | cw(42p) | cw(18p) | cw(18p) .
1    1    1    1        0    1    D    \(em2    +6
.TE
.LP
\fINote\fR
\ \(em\ Q1 is the first bit in time.
.LP
\fINote\ 2\fR
\ \(em\ Not essential for continuous carrier operation.
.LP
\fINote\ 3\fR
\ \(em\ Interchange circuits 140 and 141 are optional.
.nr PS 9
.RT
.ad r
\fBTableau 2/V.33 [T3.33], p. 21\fR
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
5.2
    \fIThreshold and response times of circuit\ 109\fR
.sp 9p
.RT
.sp 1P
.LP
5.2.l
    \fIThreshold\fR \v'3p'
.sp 9p
.RT
.LP
    \(em
    greater than \(em26\ dBm:
    circuit 109 ON
.LP
    \(em
    less than \(em33\ dBm:
    circuit 109 OFF
.PP
The condition of circuit 109 for levels between \(em26\ dBm and
\(em33\ dBm is not specified except that the signal detector shall exhibit a
hysteresis action, such that the level at which the OFF to ON transition
occurs is at least 2\ dB greater than that for the ON to OFF transition.
.sp 1P
.LP
5.2.2.
    \fIResponse times\fR \v'3p'
.sp 9p
.RT
.LP
    \(em
    ON to OFF: 40 \(+-\|10 ms:
.LP
    \(em
    OFF to ON:
.LP
    1)
     for initial equalization, circuit\ 109 must be ON prior to user data
appearing on circuit\ 104;
.LP
    2)
     for re\(hyequalization during data transfer, circuit\ 109 will be maintained
in the ON condition; during this period, circuit\ 104 may be clamped to
the binary\ 1 condition;
.bp
.LP
    3)
     after a line signal interruption that lasts more than the ON to OFF response
time:
.LP
    a)
    when no new equalization is needed, 25 \(+-\|10 ms;
.LP
    b)
     when a new equalization is needed, circuit\ 109 must be ON prior to user
data appearing on circuit\ 104.
.PP
Response times of circuit\ 109 are the times that elapse between
the connection or removal of a line signal, generated by applying binary
one to circuit\ 103, to or from the modem receive line terminals and the
appearance of the corresponding ON or OFF condition on circuit\ 109.
.PP
\fINote\fR \ \(em\ Circuit\ 109 ON to OFF response time should be suitably
chosen within the specified limits to ensure that all valid data bits have
appeared on circuit\ 104.
.RT
.sp 1P
.LP
5.3
    \fIResponse time for circuit\ 106\fR
.sp 9p
.RT
.PP
Following the complete training procedure, the time between the OFF to
ON transition of circuit\ 105 and the OFF to ON transition of circuit\
106
shall be 15\ ms \(+-\|5\ ms.
.PP
The time between the ON to OFF transition of circuit\ 105 and the ON to
OFF transition of circuit\ 106 shall be suitably chosen to ensure that
all valid signal elements have been transmitted.
.RT
.sp 2P
.LP
\fB6\fR     \fBElectrical characteristics of interchange circuits\fR
.sp 1P
.RT
.PP
6.1
Use of electrical characteristics conforming to
Recommendation\ V.28 is recommended together
with the connector pin assignment plan specified by ISO\ 2110\ [3].
.sp 9p
.RT
.sp 1P
.LP
6.2
    \fIFault condition on interchange circuits\fR
.sp 9p
.RT
.PP
(See \(sc\ 7 of Recommendation V.28 for association of the receiver
failure detection types).
.RT
.PP
6.2.l
The DTE should interpret a fault condition on circuit\ 107 as an OFF condition
using failure detection type\ 1.
.sp 9p
.RT
.PP
6.2.2
The DCE should interpret a fault condition on circuit\ 105 as an
OFF condition using failure detection type\ 1.
.PP
6.2.3
All other circuits not referred to above may use failure detection types\
0 or 1.
.sp 1P
.LP
6.3
    \fITiming arrangements\fR
.sp 9p
.RT
.PP
Clocks shall be included in the modem to provide the data terminal equipment
with transmitter signal element timing, circuit\ 114, and receiver
signal element timing, circuit\ 115. In this arrangement, the transmitter may
either run as an independent timing source or with loopback timing (transmit
timing slaved to receive timing). Loopback timing may be desirable in some
network applications.
.PP
Alternatively, the transmitter signal element timing may be originated
in the data terminal equipment and be transferred to the modem via interchange
circuit\ 113.
.RT
.sp 2P
.LP
\fB7\fR     \fBScrambler\fR
.sp 1P
.RT
.PP
A self\(hysynchronizing scramblerB/Fdescrambler having the generating
polynomial 1\ +\ x\uD\dlF261\u1\d\u8\d\ +\ x\uD\dlF261\u2\d\u3\d, shall
be included in the modem.
.PP
At the transmitter the scrambler shall effectively divide the message polynomial,
of which the input data sequence represents the coefficients in
descending order, by the scrambler generating polynomial to generate the
transmitted sequence. At the receiver the received polynomial, of which the
received data sequence represents the coefficients in descending order,
shall be multiplied by the scrambler generating polynomial to recover the
message
sequence.
.PP
The detailed scrambling and descrambling processes are described in
the Annex.
.RT
.sp 2P
.LP
\fB8\fR     \fBSynchronizing signals\fR
.sp 1P
.RT
.PP
Transmission of synchronizing signals may be initiated by the
modem.  When the receiving modem requires resynchronizing, it shall turn
circuit\ 106 OFF and generate a synchronizing signal sequence.
.bp
.PP
The synchronizing signals for all data signalling rates are divided into
four segments as in Table\ 3/V.33.
.RT
.ce
\fBH.T. [T4.33]\fR
.ce
TABLE\ 3/V.33
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
lw(48p) | cw(36p) | cw(36p) | cw(36p) | cw(36p) | cw(36p) .
    Segment 1    Segment 2  TRN    Segment 3    Segment 4    Total
_
.T&
lw(48p) | cw(36p) | cw(36p) | cw(36p) | cw(36p) | cw(36p) .
Type of line signal    Alternations ABAB    Equalizer condition pattern    Rate sequence    Scrambled all binary   ONEs    T{
Total synchronizing signal time
T}
_
.T&
lw(48p) | cw(36p) | cw(36p) | cw(36p) | cw(36p) | cw(36p) .
Number of symbol intervals    256    2976    64    48    3344
_
.T&
lw(48p) | cw(36p) | cw(36p) | cw(36p) | cw(36p) | cw(36p) .
Approximate time in ms    106    1240    27    20    1393
_
.TE
.nr PS 9
.RT
.ad r
\fBTable 3/V.33 [T4.33], p.\fR
.sp 1P
.RT
.ad b
.RT
.PP
8.1
Segment\ 1 consists of alternations between states\ A and B as
shown in Figures\ 2 and 3/V.33 for a duration of 256\ symbol intervals.
.sp 9p
.RT
.sp 1P
.LP
8.2
    \fISegment\ 2:\fR
\fIEqualizer conditioning pattern\fR
.sp 9p
.RT
.PP
The segment consists of the sequential transmission of four signal elements
A, B, C and D. These signal elements are shown in Figures\ 2/V.33 and 3/V.33.
The equalizer conditioning pattern is a pseudo\(hyrandom sequence at
4800\ bitB/Fs generated by the l\ +\ x\uD\dlF261\u1\d\u8\d\ +\ x\uD\dlF261\u2\d\u3\d
data scrambler. During segment\ 2 any differential quadrant encoding is
disabled and the
scrambled dibits are encoded as follows:
.RT
.sp 1P
.ce 1000
00 = C\ \ 01 = D\ \ 11 = A\ \ 10 = B
.ce 0
.sp 1P
.PP
With a binary 1 applied to the input, the initial state of the
scrambler shall be selected to produce the following scrambler output pattern
and corresponding signal elements:
.LP
00
01
00
01
00
01
00
01
00
01
00
01
10
01
10
01
.LP
C
D
C
D
C
D
C
D
C
D
C
D
B
D
B
D
.PP
Segment\ 2 continues for 2976 symbol intervals.
.sp 1P
.LP
8.3
    \fISegment\ 3:\fR
\fIRate signal\fR
.sp 9p
.RT
.PP
The rate signal consists of a 16\(hybit binary sequence repeated
8\ times. The sequence is defined in Table\ 4/V.33, scrambled and transmitted
at 4800\ bit/s with dibits differentially encoded as in Table\ 1B/V.33.
The
differential encoder shall be initialized using the final symbol of the
previous segment.
.PP
The first two bits and subsequent dibits of each rate sequence shall be
encoded as one signal state.
.PP
The rate signal may be used for establishing the data signalling rate between
the modems, and providing information regarding multiplexer
configuration, or other configuration information (subject to further study).
When B14\ =\ 0, only data signalling rate information is conveyed according
to
Table\ 4A/V.33. When B14\ =\ 1, the bit assignment of Table\ 4B/V.33 applies.
.PP
The minimum requirement for detection is the receipt of two
consecutive identical l6\(hybit sequences each with bits B0\(hy3, B7, B11
and B15
conforming with Table\ 4/V.33. Following the detection of the rate sequence,
the receiver shall be conditioned to receive data at the highest common
rate with the indicated multiplexer configuration.
.bp
.RT
.ce
\fBH.T. [T5.33]\fR
.ce
TABLE\ 4A/V.33
.ce
\fBBit designations\fR
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
0 0    1 0    2 0    3 0    4    5    6    7 1    8    9    10    11 \ 1    12    13    14 \ 0    15 \ 1
_
.T&
lw(48p) | lw(144p) .
B0\(hy3, B7, B11, B15    T{
For synchronizing on a received rate signal
T}
.T&
lw(48p) | lw(144p) .
B4\(hy6    T{
Not yet defined (for further study)
T}
.T&
lw(48p) | lw(144p) .
B8 \(hy3, B7, B11,  1    T{
Denotes ability to transmit and receive data at
12\|000\ bit/s (Note)
T}
.T&
lw(48p) | lw(144p) .
B9 \(hy3, B7, B11,  1    T{
Denotes ability to transmit and receive data at
14\|400\ bit/s (Note)
T}
.T&
lw(48p) | lw(144p) .
B10, B12, B13    Not yet defined (for further study)
.TE
.LP
\fINote\fR
\ \(em\ When transmitting a rate signal, the modem will transmit bits
B8 B9 equal to\ 11 or\ 01 when the data signalling rate of segment\ 4 equals
14.4\ kbit/s and B8 B9\ =\ 10 when the data signalling rate of segment\ 4 equals
12\ kbit/s.
.nr PS 9
.RT
.ad r
\fBTable 4A/V.33 [T5.33], p.\fR
.sp 1P
.RT
.ad b
.RT
.ce
\fBH.T. [T6.33]\fR
.ce
TABLE\ 4B/V.33
.ce
\fBBit designations\fR
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
0 0    1 0    2 0    3 0    4    5    6    7 1    8    9    10    11 \ 1    12    13    14 \ 0    15 \ 1
_
.T&
lw(48p) | lw(144p) .
B0\(hy3, B7, B11, B15    T{
For synchronizing on a received rate signal
T}
.T&
lw(48p) | lw(144p) .
B4, B5 \(hy3, B11,  00    T{
Denotes that B6, B10, B12, B13 define multiplexer configuration
select (Note\ 1)
T}
.T&
lw(48p) | lw(144p) .
B8 \(hy3, B7, B11,  1    T{
Denotes ability to transmit and receive data at
12\|000\ bit/s (Notes 1 and 3)
T}
.T&
lw(48p) | lw(144p) .
B9 \(hy3, B7, B11,  1    T{
Denotes ability to transmit and receive data at
14\|400\ bit/s (Notes 1 and 3)
T}
.T&
lw(48p) | lw(144p) .
B6, B10, B12, B13    T{
Multiplexer configuration select (see Note 2 and
Tables 5A, 5B/V.33)
T}
.TE
.LP

\fINote\ 1\fR
\ \(em\ Other combinations of B4, B5 may be used to denote that
B6, B8, B9, B10, B12 and B13 define other configuration information
(for further study).
.LP
\fINote\ 2\fR
\ \(em\ a)
B6, B10, B12, B13\ =
all ZEROs: Manual Mode;
.LP
b)
B6, B10, B12, B13
Binary representation of 1 through 11 (B6 = MSB, most significant bit) denotes desired multiplexer
configuration as shown in Tables\ 5A and 5B/V.33;
.LP
c)
B6, B10, B12, B13\ =
all ONEs: Remotely
Programmable Mode. If a modem is so configured it will always transmit this
pattern.
.LP
d)
B6, B10, B12, B13
The unused combinations
are available for use as manufacturer's option;
.LP
e)
It is recommended that either both modems be configured with the identical multiplexer Mode or one modem be configured in the remotely
programmable multiplexer Mode.
.LP
\fINote\ 3\fR
\ \(em\ When transmitting a rate signal, the modems will transmit bits
B8 B9 equal to\ 11 or\ 01 when the data signalling rate of segment\ 4 equals
14.4\ kbit/s and B8 B9 = 10 when the data signalling rate of segment\ 4 equals
12\ kbit/s.
.nr PS 9
.RT
.ad r
\fBTable 4B/V.33 [T6.33], p.\fR
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.sp 1P
.LP
8.4
    \fISegment 4\fR
.sp 9p
.RT
.PP
The differential encoding to be used during this segment is defined in
Table\ 1A/V.33. The differential encoder shall be initialized using the
first symbol of the previous segment. Segment\ 4 shall begin with the initial
states of the delay elements of the convolutional encoder shown in
Figure\ l/V.33 set to zero.
.PP
This segment initiates transmission at the highest rate indicated by segment\
3 according to the encoding described in \(sc\ 2.2 above with continuous
binary ONEs applied to the input of the data scrambler. The duration of
segment\ 4 is 48\ symbol intervals.  At the end of segment\ 4, circuit\ 106 is
turned ON and user data are applied to the input of the data scrambler.
.RT
.sp 2P
.LP
\fB9\fR     \fBTraining\(hyretraining procedure\fR
.sp 1P
.RT
.PP
An automatic adaptive equalizer shall be provided in the receiver.
.PP
The receiver shall incorporate a means of detecting loss of
equalization and initiating a synchronizing signal sequence in its associated
local transmitter.
.PP
The receiver shall incorporate a means of detecting a synchronizing
signal and the rate sequence from the remote transmitter and initiating a
synchronizing signal sequence in its associated local transmitter, which
may be initiated at any time during the reception of the synchronizing
signal
sequence, regardless of the state of circuit\ 105.
.PP
Either modem may initiate a synchronizing signal sequence. The
synchronizing signal is initiated when the receiver has detected a loss of
equalization, or upon detecting a change in data rate or multiplexer
configuration selection (made by a switch or by circuit\ 111). Having initiated
a synchronizing signal, the modem expects a synchronizing signal from the
remote transmitter.
.PP
Following the end of the transmitted synchronizing signal sequence, if
the modem does not receive a synchronizing signal from the remote transmitter
within a time interval equal to the maximum expected two\(hyway propagation
delay, it transmits another signal. A time interval of 1.2\ seconds is
recommended.
.PP
If the modem fails to synchronize on the received signal sequence, or fails
to detect the rate signal, or is unable to provide the requested rate,
or is transmitting at a rate higher than the requested rate, it transmits
another synchronizing signal with rate sequence and data signalling rate
conforming
with the highest common rate, provided that it had not been sending a
synchronizing sequence within the last 1.2\ seconds.
.PP
If the modem receives a synchronizing signal when it had not initiated
a synchronizing signal and the receiver properly synchronizes, it returns
only one synchronizing sequence.
.PP
\fINote\fR \ \(em\ When a synchronizing sequence is initiated due to loss of
equalization, the previous multiplexer configuration should be maintained.
.RT
.sp 2P
.LP
\fB10\fR     \fBMultiplexing \fR (See Tables 5A/V.33 and 5B/V.33)
.sp 1P
.RT
.PP
A multiplexing option may be included to combine 12\|000, 9600,
7200, 4800, and 2400\ bit/s data subchannels into a single aggregate bit
stream for transmission. Identification of the individual modulator bits
is
accomplished by assignment to the modulator as defined in \(sc\ 2.2 above.
.RT
.LP
.rs
.sp 11P
.ad r
BLANC
.ad b
.RT
.LP
.bp
.ce
\fBH.T. [T7.33]\fR
.ce
TABLE\ 5A/V.33
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) sw(12p) sw(12p) sw(12p) sw(12p) sw(12p) , ^  | ^  | ^  | ^  | c | c | c | c | c | c.
Aggregate data rate (bit/s)    Multiplex configuration    T{
Sub\(hychannel data rate (bit/s)
T}    Multiplex channel    Modulator bits
                Q1      Q2      Q3    Q4      Q5    Q6
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
14\|400    \ 1    14\|400    A    X    X    X    X    X    X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
14\|400    \ 2    12\|000 \ 2\|400    A B    X    X    X    X    X    X  X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
14\|400    \ 3    \ 9\|600 \ 4\|800    A B    X    X    X  X    X    X    X  X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
14\|400    \ 4    \ 9\|600 \ 2\|400 \ 2\|400    A B C    X    X    X  X    X    X    X  X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
14\|400    \ 5    \ 7\|200 \ 7\|200    A B    X    X  X    X    X  X    X    X  X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
14\|400    \ 6    \ 7\|200 \ 4\|800 \ 2\|400    A B C    X    X  X    X    X  X    X    X  X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
14\|400    \ 7    T{
\ 7\|200
\ 2\|400
\ 2\|400
\ 2\|400
T}    A B C D    X    X  X    X    X  X    X    X  X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
14\|400    \ 8    \ 4\|800 \ 4\|800 \ 4\|800    A B C    X    X  X    X  X    X    X  X    X  X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
14\|400    \ 9    T{
\ 4\|800
\ 4\|800
\ 2\|400
\ 2\|400
T}    A B C D    X    X  X    X  X    X    X  X    X  X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
14\|400    10    T{
\ 4\|800
\ 2\|400
\ 2\|400
\ 2\|400
\ 2\|400
T}    A B C D E    X    X  X    X  X    X    X  X    X  X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
14\|400    11    T{
\ 2\|400
\ 2\|400
\ 2\|400
\ 2\|400
\ 2\|400
\ 2\|400
T}    A B C D E F    X    X  X    X  X    X  X    X  X    T{
X
X
T}
.TE
.LP

\fINote\fR
\ \(em\ When more than one modulator bit is assigned to a sub\(hychannel, the
first bit in time of the sub\(hychannel is assigned to the first available bit in time of the modulator.
.nr PS 9
.RT
.ad r
\fBTableau 5A/V.33 [T7.33], p. 25\fR
.sp 1P
.RT
.ad b
.RT
.LP
.rs
.sp 04P
.ad r
BLANC
.ad b
.RT
.LP
.bp
.ce
\fBH.T. [T8.33]\fR
.ce
TABLE\ 5B/V.33
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) sw(12p) sw(12p) sw(12p) sw(12p) sw(12p) , ^  | ^  | ^  | ^  | c | c | c | c | c | c.
Aggregate data rate (bit/s)    Multiplex configuration    T{
Sub\(hychannel data rate (bit/s)
T}    Multiplex channel    Modulator bits
                Q1      Q2      Q3    Q4      Q5    Q6
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | lw(12p) .
12\|000    \ 1    12\|000    A    X    X    X    X    X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | lw(12p) .
12\|000    \ 2    \ 9\|600 \ 2\|400    A B    X    X    X    X    X  X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | lw(12p) .
12\|000    \ 3    \ 7\|200 \ 4\|800    A B    X    X  X    X    X  X    X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | lw(12p) .
12\|000    \ 4    \ 7\|200 \ 2\|400 \ 2\|400    A B C    X    X  X    X    X    X  X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | lw(12p) .
12\|000    \ 5    \ 4\|800 \ 4\|800 \ 2\|400    A B C    X    X  X    X    X  X    X  X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | lw(12p) .
12\|000    \ 6    T{
\ 4\|800
\ 2\|400
\ 2\|400
\ 2\|400
T}    A B C D    X    X  X    X    X  X    X  X
_
.T&
cw(42p) | cw(42p) | cw(36p) | cw(36p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | lw(12p) .
12\|000    7    T{
\ 2\|400
\ 2\|400
\ 2\|400
\ 2\|400
\ 2\|400
T}    A B C D E    X    X  X    X  X    X  X    T{
X
X
T}
.TE
.LP

\fINote\fR
\ \(em\ When more than one modulator bit is assigned to a sub\(hychannel, the
first bit in time of the sub\(hychannel is assigned to the first available bit in time of the modulator.
.nr PS 9
.RT
.ad r
\fBTableau 5B/V.33 [T8.33], p. 26\fR
.sp 1P
.RT
.ad b
.RT
.LP
.rs
.sp 19P
.ad r
BLANC
.ad b
.RT
.LP
.bp
.sp 1P
.LP
10.1
    \fIList of interchange circuits concerned with multiplexer ports\fR
.sp 9p
.RT
.ce
\fBH.T. [T9.33]\fR
.ce
TABLE\ 6/V.33
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(24p) sw(96p) | cw(36p) | cw(36p) | cw(36p) , c | c | ^ | ^ | ^ .
T{
Interchange circuits
(see Note 1)
T}    Port A    Port  B, C, D, E and F    Notes
No.    Designation
_
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | lw(36p) .
102    T{
Signal ground or common return
T}    X    X
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | lw(36p) .
103    Transmitted data    X    X
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | lw(36p) .
104    Received data    X    X
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | cw(36p) .
105    Request to send    X    X    Note 2
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | cw(36p) .
106    Ready for sending    X    X    Note 3
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | cw(36p) .
107    Data set ready    X    X
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | cw(36p) .
109    T{
Data channel received line signal detector
T}    X    X
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | cw(36p) .
111    T{
Data signalling rate selector (DTE source)
T}    X        Note 4
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | cw(36p) .
113    T{
Transmitter signal element timing (DTE source)
T}    X    X
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | cw(36p) .
114    T{
Transmitter signal element timing (DCE source)
T}    X    X
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | cw(36p) .
115    T{
Receiver signal element timing (DCE source)
T}    X    X
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | cw(36p) .
140    Loopback/Maintenance test    X    X    Note 5
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | cw(36p) .
141    Local loopback    X        Notes 5 & 6
.T&
cw(24p) | lw(96p) | cw(36p) | cw(36p) | cw(36p) .
142    Test indicator    X    X    Note 7
.TE
.LP
\fINote\ 1\fR
\ \(em\ All essential interchange circuits and any others which are provided shall comply with the functional and operational requirements of
Recommendation\ V.24. All interchange circuits indicated by\ X shall be properly terminated in the data terminal equipment and in the data circuit\(hyterminating equipment in accordance with the appropriate Recommendation for electrical
characteristics (see \(sc\ 6).
.LP
\fINote\ 2\fR
\ \(em\ Circuit 105 is not necessary for continuous carrier transmission.
The transmitted line signal will not be controlled by this interchange circuit. If needed, circuit\ 105 (when the multiplexer is present) is used to control
circuit\ 109 at the remote DCE. See \(sc\ 10.4 below.
.LP
\fINote\ 3\fR
\ \(em\ During the synchronization process of the main DCE the OFF condition of circuit\ 106 is signalled at all port interfaces.
.LP
\fINote\ 4\fR
\ \(em\ Circuit 111 is optionally present on port A. If present, circuit 111 is activated in multiplexer configuration\ 1 in the same way as if no
multiplexer were present.
.LP
\fINote\ 5\fR
\ \(em\ Circuits 140 and 141 are optional.
.LP
\fINote\ 6\fR
\ \(em\ Circuit 141 is present only on port A. When used in multiplexer
configurations other than configuration\ 1, the looping occurs on all ports.
.LP
\fINote\ 7\fR
\ \(em\ Circuit 142 is present on all ports of the multiplexer, but may be activated on an individual port basis for individual port tests. All are
activated simultaneously for entire DCE test.
.nr PS 9
.RT
.ad r
\fBTable 6/V.33 [T9.33], p.\fR
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
.sp 2
10.2
    \fITransmit buffers\fR
.sp 9p
.RT
.PP
In the transmitter of each multiplexer port, there shall be a data buffer
of suitable capacity. In this way, both phase variations and, within
certain limits, frequency deviations are absorbed.  The buffer shall be
initialized when the OFF to ON transition of circuit\ 105 occurs and may be
repositioned in the event of the buffer overflow.
.PP
\fINote\fR \ \(em\ The buffer may be initialized upon the DCE sending a
synchronizing signal.
.bp
.RT
.sp 1P
.LP
10.3
    \fITransmit port timing arrangements\fR
.sp 9p
.RT
.PP
Table 7/V.33 shows all possible combinations of port and main DCE transmit
timing clock arrangements.
.RT
.ce
\fBH.T. [T10.33]\fR
.ce
TABLE\ 7/V.33
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(80p) | cw(74p) | cw(74p) .
T{
Source of port: transmitter signal element timing (used to clock
in circuit\ 103)
T}    T{
Source of DCE: internal transmitter element timing (internal transit
clock)
T}    Port transmit buffer
_
.T&
lw(80p) | lw(74p) | lw(74p) .
    T{
Internal
(Independent timing)
T}    Not required
_
.T&
lw(80p) | lw(74p) | lw(74p) .
114 (DCE source)    T{
External\|\ua\d\u)\d
(circuit 113 of selected port)
T}    Not required
_
.T&
lw(80p) | lw(74p) | lw(74p) .
    T{
Receiver timing
(loopback timing)
T}    Not required
_
.T&
lw(80p) | lw(74p) | lw(74p) .
    T{
Internal
(Independent timing)
T}    Required
_
.T&
lw(80p) | lw(74p) | lw(74p) .
113 (DTE\|\ua\d\u)\d source)    T{
External\|\ua\d\u)\d
(Circuit 113 of selected port)
T}    T{
Required for all ports except port supplying circuit
113 to DTE
T}
_
.T&
lw(80p) | lw(74p) | lw(74p) .
    T{
Receiver timing
(loopback timing)
T}    Required
.TE
.LP
\ua\d\u)\d\ In these applications a source could also be another DCE.
.nr PS 9
.RT
.ad r
\fBTable 7/V.33 [T10.33], p.\fR
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
10.4
    \fIPort simulated circuit\ 105 to circuit\ 109 operation\fR (optional)
.sp 9p
.RT
.PP
Simulated circuits 105 to 109 operation on an individual port
interface may optionally be provided in accordance with
Recommendation\ V.13.
.RT
.ce 1000
ANNEX\ A
.ce 0
.ce 1000
(to Recommendation\ V.33)
.sp 9p
.RT
.ce 0
.ce 1000
\fBDetailed scrambling, descrambling and\fR
.sp 1P
.RT
.ce 0
.ce 1000
\fBpseudo\(hyrandom sequence generation processes\fR
.ce 0
.LP
\fR A.1
    \fIScrambling\fR
.sp 1P
.RT
.PP
The message polynomial is divided by the generating polynomial
1\ +\ x\uD\dlF261\u1\d\u8\d\ +\ x\uD\dlF261\u2\d\u3\d (see Figure\ A.1/V.33).
The coefficients of
the quotient of this division taken in descending order form the data sequence
to be transmitted. The shift register shall be preconditioned to produce
the
output pattern defined in \(sc\ 8.2 (the initial state of the scrambler
required to
.PP
generate that pattern is: 1010, 1011, 1011\ 0011, 0111, 010). The scrambler
shall be clocked at 4\ 800 Hz during segments\ 2 and 3 and shall be clocked at
the data rate during segment\ 4. During segments\ 2, 3 and 4 and during normal
data transmission, the shift register is fed with
scrambled data D\ds\u:
.RT
.sp 1P
.ce 1000
D\ds\u\ =\ D\di\u\ +\ D\ds\u\ x\uD\dlF261\u1\d\u8\d\ +\ D\ds\u\ x\uD\dlF261\u2\d\u3\d
.ce 0
.sp 1P
.LP
where D\di\uis binary one during segments\ 2 and 4 and the rate sequence
during segment\ 3.
.bp
.sp 1P
.LP
A.2
    \fIDescrambling\fR
.sp 9p
.RT
.PP
The polynomial represented by the received sequence is multiplied by the
generating polynomial (Figure\ A.2/V.33) to form the recovered message
polynomial. The coefficients of the recovered polynomial, taken in descending
order, form the output data sequence D\do\u:
.RT
.sp 1P
.ce 1000
D\do\u\ =\ D\di\u\ =\ D\ds\u\ (1\ +\ x\uD\dlF261\u1\d\u8\d\ +\ x\uD\dlF261\u2\d\u3\d)
.ce 0
.sp 1P
.LP
A.3
    \fIElements of the scrambling process\fR
.sp 9p
.RT
.PP
The polynomial 1\ +\ x\uD\dlF261\u1\d\u8\d\ +\ x\uD\dlF261\u2\d\u3\d generates
a
pseudo\(hyrandom sequence of length 2\u2\d\u3\d\ \(em\ 1\ =\ 8,388,607.
This long sequence does not require the use of a guard polynomial to prevent
the occurrence of
repeated patterns and is particularly simple to implement with integrated
circuits.
.RT
.LP
.rs
.sp 13P
.ad r
\fBFigure A\(hy1/V.33, p.\fR
.sp 1P
.RT
.ad b
.RT
.LP
.rs
.sp 13P
.ad r
\fBFigure A\(hy2/V.33, p.\fR
.sp 1P
.RT
.ad b
.RT
.sp 2P
.LP
    \fBReferences\fR
.sp 1P
.RT
.LP
[1]
     CCITT Recommendation \fICharacteristics of special quality international\fR
\fIleased circuits with special bandwidth conditioning\fR , Vol. IV,
Fascicle\ IV.2, Rec.\ M.1020.
.LP
[2]
     CCITT Recommendation \fICharacteristics of special quality international\fR
\fIleased circuits with basic bandwidth conditioning\fR , Vol. IV, Fascicle\
IV.2,
Rec.\ M.1025.
.LP
[3]
     Data communication\ \(em\ \fI25\(hypin DTEB/FDCE interface connector
and pin\fR
\fIassignments\fR , ISO\ Standard\ 2110.
.LP
.bp