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C/C++ Source or Header  |  1995-01-16  |  5.5 KB  |  176 lines
  1. /*
  2.  * include/asm-mips/mipsregs.h
  3.  *
  4.  * This file is subject to the terms and conditions of the GNU General Public
  5.  * License.  See the file "COPYING" in the main directory of this archive
  6.  * for more details.
  7.  *
  8.  * Copyright (C) 1994 by Ralf Baechle
  9.  */
  10.  
  11. #ifndef __ASM_MIPS_MIPSREGS_H
  12. #define __ASM_MIPS_MIPSREGS_H
  13.  
  14. /*
  15.  * The following macros are especially useful for __asm__
  16.  * inline assembler.
  17.  */
  18.  
  19. #ifndef __STR
  20. #define __STR(x) #x
  21. #endif
  22. #ifndef STR
  23. #define STR(x) __STR(x)
  24. #endif
  25.  
  26. /*
  27.  * On the R2000/3000 load instructions are not interlocked -
  28.  * we therefore sometimes need to fill load delay slots with a nop
  29.  * which are useless for >=R4000.
  30.  *
  31.  * FIXME: Don't know about R6000
  32.  */
  33. #if !defined (__R4000__)
  34. #define FILL_LDS nop
  35. #else
  36. #define FILL_LDS
  37. #endif
  38.  
  39. /*
  40.  * Coprocessor 0 register names
  41.  */
  42. #define CP0_INDEX $0
  43. #define CP0_RANDOM $1
  44. #define CP0_ENTRYLO0 $2
  45. #define CP0_ENTRYLO1 $3
  46. #define CP0_CONTEXT $4
  47. #define CP0_PAGEMASK $5
  48. #define CP0_WIRED $6
  49. #define CP0_BADVADDR $8
  50. #define CP0_COUNT $9
  51. #define CP0_ENTRYHI $10
  52. #define CP0_COMPARE $11
  53. #define CP0_STATUS $12
  54. #define CP0_CAUSE $13
  55. #define CP0_EPC $14
  56. #define CP0_PRID $15
  57. #define CP0_CONFIG $16
  58. #define CP0_LLADDR $17
  59. #define CP0_WATCHLO $18
  60. #define CP0_WATCHHI $19
  61. #define CP0_XCONTEXT $20
  62. #define CP0_ECC $26
  63. #define CP0_CACHEERR $27
  64. #define CP0_TAGLO $28
  65. #define CP0_TAGHI $29
  66. #define CP0_ERROREPC $30
  67.  
  68. /*
  69.  * Values for PageMask register
  70.  */
  71. #define PM_4K   0x00000000
  72. #define PM_16K  0x00006000
  73. #define PM_64K  0x0001e000
  74. #define PM_256K 0x0007e000
  75. #define PM_1M   0x001fe000
  76. #define PM_4M   0x007fe000
  77. #define PM_16M  0x01ffe000
  78.  
  79. /*
  80.  * Values used for computation of new tlb entries
  81.  */
  82. #define PL_4K   12
  83. #define PL_16K  14
  84. #define PL_64K  16
  85. #define PL_256K 18
  86. #define PL_1M   20
  87. #define PL_4M   22
  88. #define PL_16M  24
  89.  
  90. /*
  91.  * Compute a vpn/pfn entry for EntryHi register
  92.  */
  93. #define VPN(addr,pagesizeshift) ((addr) & ~((1 << (pagesizeshift))-1))
  94. #define PFN(addr,pagesizeshift) (((addr) & ((1 << (pagesizeshift))-1)) << 6)
  95.  
  96. /*
  97.  * Macros to access the system control coprocessor
  98.  */
  99. #define read_32bit_cp0_register(source)                                        \
  100. ({ int __res;                                                                  \
  101.         __asm__ __volatile__(                                                  \
  102.         "mfc0\t%0,"STR(source)                                                 \
  103.         : "=r" (__res));                                                       \
  104.         __res;})
  105.  
  106. #define read_64bit_cp0_register(source)                                        \
  107. ({ int __res;                                                                  \
  108.         __asm__ __volatile__(                                                  \
  109.         "dmfc0\t%0,"STR(source)                                                \
  110.         : "=r" (__res));                                                       \
  111.         __res;})
  112.  
  113. #define write_32bit_cp0_register(register,value)                               \
  114.         __asm__ __volatile__(                                                  \
  115.         "mtc0\t%0,"STR(register)                                               \
  116.         : : "r" (value));
  117.  
  118. /*
  119.  * Inline code for use of the ll and sc instructions
  120.  *
  121.  * FIXME: This instruction is only available on MIPS ISA >=3.
  122.  * Since these operations are only being used for atomic operations
  123.  * the easiest workaround for the R[23]00 is to disable interrupts.
  124.  */
  125. #define load_linked(addr)                                                      \
  126. ({                                                                             \
  127.     unsigned int __res;                                                    \
  128.                                                                                \
  129.     __asm__ __volatile__(                                                  \
  130.     "ll\t%0,(%1)"                                                          \
  131.     : "=r" (__res)                                                         \
  132.     : "r" ((unsigned int) (addr)));                                        \
  133.                                                                                \
  134.     __res;                                                                 \
  135. })
  136.  
  137. #define store_conditional(addr,value)                                          \
  138. ({                                                                             \
  139.     int    __res;                                                         \
  140.                                                                                \
  141.     __asm__ __volatile__(                                                  \
  142.     "sc\t%0,(%2)"                                                          \
  143.     : "=r" (__res)                                                         \
  144.     : "0" (value), "r" (addr));                                            \
  145.                                                                                \
  146.     __res;                                                                 \
  147. })
  148.  
  149. /*
  150.  * Bitfields in the cp0 status register
  151.  *
  152.  * Refer to MIPS R4600 manual, page 5-4 for explanation
  153.  */
  154. #define ST0_IE  (1   <<  0)
  155. #define ST0_EXL (1   <<  1)
  156. #define ST0_ERL (1   <<  2)
  157. #define ST0_KSU (3   <<  3)
  158. #define ST0_UX  (1   <<  5)
  159. #define ST0_SX  (1   <<  6)
  160. #define ST0_KX  (1   <<  7)
  161. #define ST0_IM  (255 <<  8)
  162. #define ST0_DE  (1   << 16)
  163. #define ST0_CE  (1   << 17)
  164. #define ST0_CH  (1   << 18)
  165. #define ST0_SR  (1   << 20)
  166. #define ST0_BEV (1   << 22)
  167. #define ST0_RE  (1   << 25)
  168. #define ST0_FR  (1   << 26)
  169. #define ST0_CU  (15  << 28)
  170. #define ST0_CU0 (1   << 28)
  171. #define ST0_CU1 (1   << 29)
  172. #define ST0_CU2 (1   << 30)
  173. #define ST0_CU3 (1   << 31)
  174.  
  175. #endif /* __ASM_MIPS_MIPSREGS_H */
  176.