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Text File | 1995-06-16 | 32.7 KB | 1,487 lines

;+ -to IDEFS::Main.$.Proto.Disassem -module -quit R0 RN 0 R1 RN 1 R2 RN 2 R3 RN 3 R4 RN 4 R5 RN 5 R6 RN 6 R7 RN 7 R8 RN 8 R9 RN 9 R10 RN 10 R11 RN 11 R12 RN 12 R13 RN 13 R14 RN 14 PC RN 15 CP15 CP 15 C0 CN 0 XOS_WriteS * &20001 XOS_Write0 * &20002 XOS_NewLine * &20003 XOS_CLI * &20005 XOS_Module * &2001E XOS_BinaryToDecimal * &20028 XOS_SWINumberToString * &20038 XOS_ReadArgs * &20049 XOS_ConvertHex2 * &200D1 XOS_ConvertHex4 * &200D2 XOS_ConvertHex6 * &200D3 XOS_ConvertHex8 * &200D4 XOS_ConvertInteger4 * &200DC ; Token mask, test, token string ; For instruction templates MACRO $l Token $m,$v,$t $l & &$m, &$v = (:LEN:"$t"+13) :AND: -4 = "$t", 0 ALIGN MEND GBLA flag__b MACRO $l FlagBit $bit [ "$bit" > "" flag__b SETA $bit ] $l * 1:SHL:flag__b flag__b SETA flag__b + 1 MEND ^ 0,R12 ; Workspace prev # 8 flags # 4 adrlx # 4 adrlx_f # 4 buffer # 0 # 256-:INDEX:buffer size # 0 buffptr * :INDEX:buffer flag_stack FlagBit 0 flag_apcs FlagBit flag_lfmstack FlagBit flag_lfs FlagBit flag_quoteswis FlagBit flag_usedcd FlagBit flag_usevdu FlagBit flag_andeqasdcd FlagBit flag_useadrl FlagBit flag_useadrw FlagBit flag_arm6 * 1:SHL:31 ; Now some actual code... start & 0 & :INDEX:init & :INDEX:exit & 0 & :INDEX:title & :INDEX:help & :INDEX:commands & 0 title = "Disassembler",0 help = "Disassembler",9,"0.18 (16 Jun 1995)",0 memoryflags_help = "*",27,0," allows you",27,"(set various MemoryI",27,16 = "Debugger_Disassemble features. Available switches:",13 = 9,"-FDwithR13 <f>",9,"use FD with R13, eg. STMDB R13 -> STMFD R13",13 = 9,"-APCS <f>",9,"use APCS-R register set",13 = 9,"-LFMstack <f>",9,"use stack nota",27,9," with LFM & SFM where possible" = 13 = 9,"-LFS <f>",9,"use LFS",27,16,"SFS in preference",27,"(LFM & SFM",13 = 9,"-QuoteSWIs <f>",9,"put quotes around SWI ",27,11,"s",13 = 9,"-UseDCD <f>",9,"use DCD instead of 'Undefined instruc",27,9,"'",13 = 9,"-UseVDU <f>",9,"use VDU x instead of SWI OS_WriteI+x",13 = 9,"-ANDEQasDCD <f>",9,"use DCD instead of 'ANDEQ'",27,16,"similar",13 = 9,"-UseADRL <f>",9,"use ADRL (ADRX) instead of ADR + ADD/SUB (+ ADD/SUB)" = 13 = 9,"-UseADRW <f>",9,"use ADRW, LDRW, STRW for R12±m & [R12,#m]",13 = "where <f>",27,")""0"" or ""N"" (off), or ""1"" or ""Y"" (on).",13 = "Use *",27,0," on its own",27,"(display",27,2,27,5," state.",13 memoryflags_syn = 27,1," [<switches>]",0 dism_help = "The ",27,0," module provides a new, fully compatible, version of " = "Debugger_Disassemble by patching into",27,2,"Debugger module. This " = "affects *MemoryI",27,16,"applica",27,9,"s such as !Zap.",13,13 = "The ARM7 instruc",27,9," set",27,")recognised,",27,16,"flagged where " = "appropriate with ""ARMx or later"".",13,13 = "Differences: unrecognised SWIs are given by ",27,13,";",27,2,"L",27,16 = "T flags for LDC",27,16,"STC are reversed",27,"(avoid confusion with",27 = 2,"LT condi",27,9,"; and UMULL",27,16,"SMULL become UMUL",27,16,"SMUL " = "respectively (to keep them",27,"(less than 8 characters with condi",27,9 = 27,16,"S flag).",13,0 rmfaster = "RMFaster " debug = "Debugger",0 commands = "DisassemblerFlags",0 ALIGN & :INDEX:memoryflags & &FF0000 & :INDEX:memoryflags_syn & :INDEX:memoryflags_help = "Disassembler",0 ALIGN & 0,0,0,:INDEX:dism_help & 0 init STMFD R13!,{R14} ; Init module ADR R0,rmfaster SWI XOS_CLI ; RMFaster Debugger (ignoring any error) MOV R0,#18 ADR R1,debug SWI XOS_Module ; Find Debugger module, exit if failed ADRVS R0,initfailed LDMVSFD R13!,{PC} MOV R8,R3 ; Claim workspace MOV R0,#6 MOV R3,#:INDEX:size SWI XOS_Module LDMVSFD R13!,{PC} STR R2,[R12] STR R2,workspace MOV R0,#0 ; Initialise workspace wipe SUBS R3,R3,#4 STRPL R0,[R2,R3] BPL wipe LDR R0,[R8,#32] ; Patch into SWI code... LDR R1,[R0,R8]! ; find address ADD R0,R0,#4 ADR R4,swijump STMIA R4,{R0,R8} ; store data for when this module RMKilled STR R1,firstinstr ADR R1,swihandler ; calculate branch offset SUB R1,R1,R0 SUB R1,R1,#4 MOV R1,R1,LSL #6 ; make branch instruction MOV R1,R1,LSR #8 ORR R1,R1,#&EA000000 STR R1,[R0,#-4] ; store it LDR R0,[R8,#-4] ; Module length SUB R0,R0,#4 MOV R1,R8 LDR R3,searchfor BIC R4,R3,#255 search SUBS R0,R0,#4 ; Search for 'print Rn' MOVEQ R1,#0 ; Set address to 0 if not found BEQ nomatch LDR R2,[R1],#4 TEQ R2,R3 LDREQ R2,[R1,#8] TEQEQ R2,R4 BNE search nomatch STR R1,rnameaddr ; Store address TEQ R1,#0 ; Found? ADRNE R0,renamecode ; If so, replace SWI with BL to my code SUBNE R0,R0,R1 SUBNE R0,R0,#4 MOVNE R0,R0,LSL #6 MOVNE R0,R0,LSR #8 ORRNE R0,R0,#&EB000000 STRNE R0,[R1,#-4] params MOV R0,R10 ; Decode parameters passed in by OS_Module MOV R1,#0 BL memoryflags1 ; ignoring errors MOV R0,#4 ; Which ARM? ADR R2,undefid ; Need to trap undefined instruction SUB R2,R2,#12 ; in case ARM2 or ARM250 MOV R2,R2,LSR #2 ORR R2,R2,#&EA000000 LDR R1,[R0] STR R2,[R0] ; = SWP R1,R2,[R0] MOV R2,#&200 ; ID = ARM2 if next instruction 'undefined' MRC CP15,0,R2,C0,C0 ; ARM ID undefid STR R1,[R0] ; Restore trap AND R2,R2,#&FF00 ; Get part type [top 8 bits of if >=ARM6] CMP R2,#&600 LDRHS R2,flags ORRHS R2,R2,#flag_arm6 ; Set 'ARM6' flag if ARM6 or later STRHS R2,flags LDMFD R13!,{PC}^ searchfor ; Code to search for in the Debugger module SWI XOS_BinaryToDecimal initfailed & 0 = "Failed to install new Debugger_Disassemble",0 ALIGN exit STMFD R13!,{R14} ; When RMKilled MOV R1,#0 STR R1,workspace ; Reset... MOV R0,#18 ADRL R1,debug SWI XOS_Module ; Find Debugger BVS released ; Killed? ADR R4,swijump LDMIA R4,{R0,R2} TEQ R2,R3 ; Or moved? BNE released TEQ R1,#0 ; If not... LDRNE R1,firstinstr ; Restore SWI code STRNE R1,[R0,#-4] LDR R1,rnameaddr ; Restore 'print Rn' code TEQ R1,#0 LDRNE R0,searchfor STRNE R0,[R1,#-4] released MOV R0,#7 LDR R2,[R12] SWI XOS_Module MOV R0,#0 STR R0,[R12] LDMFD R13!,{PC}^ swijump & 0,0 workspace & 0 rnameaddr & 0 swi_flags STMFD R13!,{R14} ; Debugger_63 LDR R12,workspace LDR R14,flags ; flags = (flags BIC R0) EOR R1 BIC R0,R14,R0 EOR R1,R0,R1 ; Returns R0 = old flags, R1 = new flags STR R1,flags MOV R0,R14 LDMFD R13!,{PC}^ renamecode STMFD R13!,{R12,R14} LDR R12,workspace LDR R14,flags TST R14,#flag_apcs BNE dorename SWI XOS_BinaryToDecimal LDMFD R13!,{R12,PC} dorename MOV R14,#8 STRB R14,[R1] ADR R14,apcs_names LDR R2,[R14,R0,LSL #1]! STRB R2,[R1,#1] MOV R2,R2,LSR #8 STRB R2,[R1,#2] MOV R2,#0 CMP R0,#9 STRGTB R2,[R1,#4] MOVGT R2,#" " STRB R2,[R1,#3] MOVGT R2,#4 MOVLE R2,#3 LDMFD R13!,{R12,PC}^ tab SUB R0,R8,R12 CMP R0,#buffptr+8 ; Tabulate MOVLT R1,#buffptr+8 ; Tab stops set at columns 8 and 27 MOVGE R1,#buffptr+27 CMP R0,#buffptr+27 ADDGE R1,R0,#1 ADD R1,R1,R12 MOV R0,#" " tabloop STRB R0,[R8],#1 TEQ R8,R1 BNE tabloop MOVS PC,R14 copy STMFD R13!,{R2,R14} ; Copy string, leaving R8 -> null copy_lp LDRB R2,[R0],#1 STRB R2,[R8],#1 TEQ R2,#0 BNE copy_lp SUB R8,R8,#1 LDMFD R13!,{R2,PC}^ regno LDRB R1,[R8,#-1] ; Register number or constant (0 to 15) TEQ R1,#"R" ; Is it an ARM register? BNE regnotr LDR R1,flags TEQ R0,#15 ; Is it R15 (and not APCS-R names)? TSTEQ R1,#2 BEQ is_pc CMP R0,#8 ; Is it in range R8..R14? MOVGE R5,R0 ; If so, flag it for later TST R1,#2 ; Are we using APCS-R names? BEQ regnotr ADR R1,apcs_names ; If so, write register name LDR R0,[R1,R0,LSL #1]! STRB R0,[R8,#-1] ; overwriting the "R" already there MOV R0,R0,LSR #8 STRB R0,[R8],#1 MOVS PC,R14 apcs_names = "a1a2a3a4v1v2v3v4v5v6slfpipsplrpc" regnotr ADD R0,R0,#"0" ; Store number CMP R0,#"9" MOVGT R1,#"1" STRGTB R1,[R8],#1 SUBGT R0,R0,#10 STRB R0,[R8],#1 MOVS PC,R14 is_pc MOV R0,#"P" ; Store R15 as PC STRB R0,[R8,#-1] ; overwriting "R" with "P" MOV R0,#"C" STRB R0,[R8],#1 MOVS PC,R14 undefined LDR R1,flags ; Undefined instruction TST R1,#flag_usedcd ; Use "Undefined" or "DCD"? ADREQ R1,undef ; "Undefined" MOVEQ R2,#useofnv-undef LDMEQFD R13!,{R0,R3-R12,PC}^ usedcd ADR R0,dcd ; "DCD" ADR R8,buffer BL copy MOV R0,R10 MOV R1,R8 MOV R2,#9 SWI XOS_ConvertHex8 ADR R1,buffer SUB R2,R8,R12 SUB R2,R2,#buffptr LDMFD R13!,{R0,R3-R12,PC}^ undef = "Undefined instruction",0 dcd = "DCD &",0 useofnv = "; *** Use of NV",0 not8_14 = "; *** Not R8-R14",0 cdp_swi = "; *** SWI after CDP",0 ALIGN ; "append" always means to disassembled string testnv ADR R0,prev ; NV test, and tests based on previous instr. LDMIA R0,{R2,R3} STMIA R0,{R10,R11} MOV R0,R10,LSR #28 CMP R0,#15 ; Is NV used? BLEQ tab ADREQ R0,useofnv BLEQ copy ; If so, append warning and exit BEQ nomasks ADD R3,R3,#4 ; Was last instruction disassembled TEQ R3,R11 ; immediately before this one? BNE nomasks ; If not, exit CMP R5,#0 BEQ trycdp ADR R9,maskp ; R8..R14 used after TSTP/TEQP/CMPP/CMNP ? LDMIA R9!,{R0,R1} AND R0,R2,R0 TEQ R0,R1 BLEQ tab ADREQ R0,not8_14 ; If so, append warning BLEQ copy trycdp ADR R9,maskcdp ; SWI after CDP ? LDMIA R9!,{R0,R1} AND R0,R2,R0 TEQ R0,R1 ANDEQ R0,R10,#&F000000 TEQEQ R0,#&F000000 BLEQ tab ADREQ R0,cdp_swi ; If so, append warning BLEQ copy nomasks ADR R1,buffer SUB R2,R8,R12 SUB R2,R2,#buffptr LDMFD R13!,{R0,R3-R12,PC}^ maskp & &D90F000, &110F000 ; R8..R14 test maskcdp & &F000010, &E000000 ; CDP/SWI test swihandler TEQ R11,#0 ; Replacement for Debugger_Disassemble BEQ disasm TEQ R11,#63 ; Extra SWI (Debugger_63) for flag toggling BEQ swi_flags firstinstr & 0 LDR PC,swijump ; (passing on others to the Debugger module) disasm STMFD R13!,{R0,R3-R12,R14} MOV R10,R0 ; word MOV R11,R1 ; address LDR R12,workspace LDMIA R12,{R0,R1} ; Special case for ADRL/ADRX ADD R1,R1,#4 TEQ R1,R11 BLEQ adrlchk MOV R0,#0 STR R0,adrlx_f MOV R1,R10,LSL #20 ; Special case for ANDEQ & similar MOV R1,R1,LSR #20 ANDS R0,R10,#&FF00000 TEQNE R0,#&200000 ; trapping AND, EOR, ORR, BIC TEQNE R0,#&1800000 ; with same register for both sources TEQNE R0,#&1C00000 ; and no shift ANDEQ R9,R10,#&F0000 TEQEQ R1,R9,LSR #16 BEQ andeq TEQ R0,#&1A00000 ; and MOV and MVN with same register TEQNE R0,#&1E00000 ; for both source and destination, no shift ANDEQ R9,R10,#&F000 TEQEQ R1,R9,LSR #12 BEQ moveq gofind LDR R9,flags TST R9,#flag_usevdu ; 'VDU' flag set? ADREQL R9,instructions ; Point to instruction templates list ADRNEL R9,withvdu ; including VDU if selected find LDMIA R9,{R0-R2} ; Search list ANDS R2,R2,#255 BEQ undefined ; Undefined instruction if not in list AND R0,R0,R10 TEQ R0,R1 ; Use mask to see if this is it ADDNE R9,R9,R2 BNE find ; If not, try next template LDRB R0,[R9,#9]! ; Is template string = ""? TEQ R0,#0 BEQ undefined ; If so, is undefined instruction godecode MOV R5,#0 ; Set R8..R14 flag to FALSE MOV R6,#0 ; Set offset flag to 0 ADR R8,buffer ; Start of buffer decode LDRB R0,[R9],#1 ; Get next char from template string STRB R0,[R8] ; Append TEQ R0,#0 BEQ testnv ; End of string? If so, check NV and flags TEQ R0,#32 BLEQ tab ; Space = tab BEQ decode SUBS R1,R0,#"¡" ADDMI R8,R8,#1 ADDPL PC,PC,R1,LSL #2 B decode B mul_check ; ¡ MUL - Rd=Rm or Rd=PC ? B minus ; ¢ sign for load/store instructions B ld_st ; £ LD or ST B psr_user ; ¤ "^" flag B f_0to2 ; ¥ FP reg B b_21to23 ; ¦ Constant B r_8to11 ; § R reg B byte ; ¨ "B" flag B condition ; © B r_12to15 ; ª B precision ; « FP precision, S/D/E/P B f_12to14 ; ¬ B f_16to18 ; (note: code 173) B f_0to2orconst ; ® FP reg or constant B const ; ¯ ARM constant for MOV etc. B branch ; ° Address B stack ; ± Stack type B reglist ; ² Register list for stack instructions B r_16to19 ; ³ B offset12 ; ´ Offset for LDR/STR B pflag ; µ "P" flag B swi ; ¶ SWI name or number B psr ; · CPSR/SPSR B sflag ; ¸ "S" flag B tflag ; ¹ "T" flag B r_0to3 ; º B round ; » FP rounding, <blank>/P/M/Z B writeback ; ¼ "!" flag B psr_part ; ½ Which part of CPSR/SPSR to update B offset8 ; ¾ Offset for LDF/STF/LDC/STC B shift ; ¿ LSL/LSR/ASR/ROR/RRX B numregs ; À Number of registers for LFM/SFM B c_5to7 ; Á Constant for CDP/MCR/MRC B pc_offset12 ; Â [PC,#offset] -> address for LDR/STR B pc_offset8 ; Ã [PC,#offset] -> address for LDF etc. B offsetis ; Ä ; =offset B b_20to23 ; Å Constant for CDP B lflag ; Æ "L" flag B cache ; Ç Cache registers B adr ; È ADR address B adrl ; É ADRL/ADRX address B lfm_sfm ; Ê LFM/SFM - which format (token string) B lfs_sfs ; Ë LFS/SFS reg list B arith ; Ì AND/EOR/.../SBC/RSC B test ; Í Compare, move, ORR, BIC B fparith ; Î FP binary (ADF etc) B fparithunary ; Ï FP unary (MVF etc) B fptrans ; Ð FP/ARM transfer (WFS etc) B fpcompare ; Ñ FP compare B mull ; Ò ARM7 long multiply B arm250orlater ; Ó ARM250 B arm6orlater ; Ô ARM6 B arm7orlater ; Õ ARM7 B char ; Ö VDU (OS_WriteI substitute) B r12offset ; × 'W' option validation (1st char only) B adrwoff ; Ø ADRW constant B ldrwoff ; Ù LDRW/STRW constant adrl_template = "ADR©L Rª,&É",0 adrx_template = "ADR©X Rª,&É",0 ALIGN adrlchk LDR R9,adrlx_f SUB R9,R9,#1 CMP R9,#1 MOVHIS PC,R14 AND R9,R10,#&0FF00000 TEQ R9,#&02400000 TEQNE R9,#&02800000 ANDEQ R1,R10,#&F000 ANDEQ R2,R10,#&F0000 ANDEQ R9,R0,#&F000 TEQEQ R1,R2,LSR #4 TEQEQ R1,R9 MOVEQ R9,R10,LSR #28 MOVEQ R1,R0,LSR #28 TEQEQ R1,R9 MOVNES PC,R14 LDR R9,adrlx_f TEQ R9,#1 ADREQ R9,adrl_template ADRNE R9,adrx_template B godecode moveq TEQ R1,#0 ADREQ R9,nop_template BEQ godecode andeq LDR R9,flags TST R9,#flag_andeqasdcd BEQ gofind LDR R9,movpcpc TEQ R9,R10,LSL #4 BNE usedcd B gofind movpcpc & &1A0F00F0 ; (MOV PC,PC) :SHL: 4 nop_template = "NOP©",0 ALIGN psr_user TST R10,#1:SHL:22 ; "^" flag BEQ decode MOV R0,#"^" STRB R0,[R8],#1 AND R0,R10,#3:SHL:21 TEQ R0,#3:SHL:21 TSTEQ R10,#1:SHL:15 BLEQ tab ADREQ R0,wrbk_user ; Append comment if ! and ^ and no R15 BLEQ copy B decode wrbk_user = "; *** ! and ^",0 is_st = "ST",0 is_ld = "LD",0 ALIGN ld_st TST R10,#1:SHL:20 ; LD or ST ADREQ R0,is_st ADRNE R0,is_ld copy_x BL copy B decode f_0to2 AND R0,R10,#7 ; FP register regno_x BL regno B decode b_21to23 MOV R0,R10,LSR #21 ; Constant AND R0,R0,#7 B regno_x r_8to11 MOV R0,R10,LSR #8 ; ARM register AND R0,R0,#15 B regno_x byte TST R10,#1:SHL:22 ; "B" flag MOVNE R0,#"B" STRNEB R0,[R8],#1 B decode condition MOV R0,R10,LSR #28 ; Condition code TEQ R0,#&E ADRNE R1,conds LDRNEB R0,[R1,R0,LSL #1]! STRNEB R0,[R8],#1 LDRNEB R0,[R1,#1] STRNEB R0,[R8],#1 B decode conds = "EQNECSCCMIPLVSVCHILSGELTGTLEALNV" r_12to15 MOV R0,R10,LSR #12 ; ARM register AND R0,R0,#15 B regno_x precision AND R0,R10,#&F000000 TEQ R0,#&E000000 ; FP precision MOVEQ R0,R10,LSR #7 BICEQ R0,R0,#&FE BICEQ R0,R0,#&F00 ORREQ R0,R0,R0,LSR #11 MOVNE R0,R10,LSR #15 BICNE R0,R0,#&7E ORRNE R0,R0,R0,LSR #6 AND R0,R0,#3 ADR R1,precs LDRB R0,[R1,R0] STRB R0,[R8],#1 B decode precs = "SDEP" f_12to14 MOV R0,R10,LSR #12 ; FP register AND R0,R0,#7 B regno_x f_16to18 MOV R0,R10,LSR #16 ; FP register AND R0,R0,#7 B regno_x f_0to2orconst AND R0,R10,#7 ; FP register or constant TST R10,#8 MOVEQ R1,#"F" MOVNE R1,#"#" STRB R1,[R8],#1 BEQ regno_x ADR R1,fpconsts ADD R0,R1,R0,LSL #2 B copy_x fpconsts = "0.0",0, "1.0",0, "2.0",0, "3.0",0 = "4.0",0, "5.0",0, "0.5",0, "10.0",0 ALIGN const AND R0,R10,#255 ; ARM constant for MOV etc. MOV R1,R10,LSR #7 AND R1,R1,#30 MOV R0,R0,ROR R1 vdu_com CMP R0,#9 ; 0 to 9 : just append digit ADDLS R1,R0,#"0" MOVHI R1,#"&" ; or "&" if > 9 STRB R1,[R8],#1 BLS decode MOV R7,R0 MOV R1,R8 MOV R2,#9 CMP R0,#&10000 ; >= 65536 - 8 digit hex BHS hex8 TST R0,#&FF00 ; >= 256 - 4 digit hex BNE hex4 SWI XOS_ConvertHex2 ; else - 2 digit hex MOV R8,R1 equals CMP R7,#8192 ; Is const < 8192 ? BHS decode BL tab ; If so, append comment... ADR R0,comment BL copy CMP R7,#127 CMPNE R7,#31 RSBHIS R0,R7,#256 ; If <256 and is printable, use ; ="<chr>" BLS notchar MOV R0,#34 STRB R0,[R8],#1 STRB R7,[R8],#1 STRB R0,[R8],#1 B decode notchar MOV R0,R7 ; Otherwise use ; =<decimal> MOV R1,R8 MOV R2,#9 SWI XOS_ConvertInteger4 MOV R8,R1 B decode comment = "; =",0 hex4 SWI XOS_ConvertHex4 MOV R8,R1 B equals hex8 SWI XOS_ConvertHex8 MOV R8,R1 B equals branch BIC R0,R10,#&FF000000 MOV R0,R0,LSL #8 ; Convert branch offset into address ADD R1,R11,#8 ADD R0,R1,R0,ASR #6 BIC R0,R0,#&FC000003 address MOV R1,R8 MOV R2,#9 SWI XOS_ConvertHex8 MOV R8,R1 B decode stack MOV R0,R10,LSR #23 ; Decode stack type AND R0,R0,#3 LDR R1,flags TST R1,#1 ; Is the R13 flag set? BEQ noR13 MOV R1,R10,LSR #16 AND R1,R1,#15 TEQ R1,#13 ; Is R13 the base register? BNE noR13 TST R10,#1:SHL:20 ADD R0,R0,#4 ; if STM, point to STM stack types ADDNE R0,R0,#4 ; similarly for LDM noR13 ADR R1,stacks ; Any of R13 conditions false LDRB R0,[R1,R0,LSL #1]! STRB R0,[R8],#1 ; Append stack type name LDRB R0,[R1,#1] STRB R0,[R8],#1 B decode stacks = "DAIADBIB" ; normal = "EDEAFDFA" ; STM = "FAFDEAED" ; LDM reglist MOV R2,R10,LSL #16 ; Register list for LDM/STM MOVS R2,R2,LSR #16 ; Output is of the form "R0,R1,R3-R5,PC" BEQ decode MOV R3,#0 regloop MOVS R2,R2,LSR #1 BCC nextreg MOV R0,#"R" STRB R0,[R8],#1 MOV R0,R3 BL regno BEQ decode AND R0,R2,#3 TEQ R0,#3 MOVEQ R0,#"-" MOVNE R0,#"," STRB R0,[R8],#1 BNE nextreg range MOVS R2,R2,LSR #1 ADDCS R3,R3,#1 BCS range MOV R2,R2,LSL #1 MOV R0,#"R" STRB R0,[R8],#1 MOV R0,R3 BL regno MOVNE R0,#"," STRNEB R0,[R8],#1 nextreg ADD R3,R3,#1 CMP R3,#16 BLT regloop B decode r_16to19 MOV R0,R10,LSR #16 ; ARM register AND R0,R0,#15 B regno_x offset12 MOV R0,R10,LSL #20 ; Offset for LDR/STR MOV R0,R0,LSR #20 offset CMP R0,#10 ; Common offset code ADDLT R0,R0,#"0" STRLTB R0,[R8],#1 ; 0 to 9? Append digit BLT decode MOV R6,R0 ; Copy offset to offset flag MOV R1,R8 MOV R2,#9 ; Else append as hex SWI XOS_ConvertHex4 MOV R2,#"&" ; Overwrite first "0" with "&" STRB R2,[R0] ; (we end up with something like &123) MOV R8,R1 B decode pflag AND R0,R10,#&F000 ; "P" flag TEQ R0,#&F000 MOVEQ R0,#"P" STREQB R0,[R8],#1 B decode swi BIC R0,R10,#&FF000000 MOV R1,R8 ; SWI name LDR R2,flags TST R2,#flag_quoteswis MOVNE R2,#34 ; Put quote if required STRNEB R2,[R1],#1 MOV R2,#224 MOV R7,R1 SWI XOS_SWINumberToString MOV R1,R7 LDRB R0,[R1] TEQ R0,#"X" ADDEQ R1,R1,#1 ADR R0,swi_user ; If "User", "OS_Undefined" or their X forms BL compare ; we use the SWI number instead ADRNE R0,swi_undef BLNE compare BEQ swinum ADD R8,R8,R2 LDR R2,flags TST R2,#flag_quoteswis SUBEQ R8,R8,#1 MOVNE R2,#34 STRNEB R2,[R8],#1 B decode swinum MOV R0,#"&" ; Use the SWI number instead STRB R0,[R8],#1 BIC R0,R10,#&FF000000 MOV R1,R8 MOV R2,#9 SWI XOS_ConvertHex6 MOV R8,R1 B decode compare STMFD R13!,{R0-R3,R14} ; String comparison (R0, R1) cploop LDRB R2,[R0],#1 ; Returns NE or EQ LDRB R3,[R1],#1 TEQ R2,R3 LDMNEFD R13!,{R0-R3,PC} TEQ R2,#0 BNE cploop LDMFD R13!,{R0-R3,PC} swi_user = "User",0 swi_undef = "OS_Undefined",0 cpsr = "CPSR",0 spsr = "SPSR",0 ALIGN psr TST R10,#1:SHL:22 ; Which PSR to use for MSR/MRS ADREQ R0,cpsr ADRNE R0,spsr B copy_x sflag TST R10,#1:SHL:20 ; "S" flag MOVNE R0,#"S" STRNEB R0,[R8],#1 B decode tflag TST R10,#1:SHL:21 ; "T" flag MOVNE R0,#"T" STRNEB R0,[R8],#1 B decode r_0to3 AND R0,R10,#15 ; ARM register B regno_x round MOV R0,R10,LSR #5 ; FP rounding type ANDS R0,R0,#3 ADRNE R1,rndchr LDRNEB R0,[R1,R0] STRNEB R0,[R8],#1 B decode rndchr = 0,"PMZ" writeback TST R10,#1:SHL:21 ; "!" flag MOVNE R0,#"!" STRNEB R0,[R8],#1 B decode psr_part MOV R0,R10,LSR #16 ; PSR part to use for MSR/MRS AND R0,R0,#15 ADR R1,psr_pnames ADD R1,R1,R0,LSL #1 ADD R0,R1,R0,LSL #2 B copy_x psr_pnames = "_0000",0, "_ctl",0,0, "_0010",0, "_0011",0 = "_0100",0, "_0101",0, "_0110",0, "_0111",0 = "_flg",0,0, "_all",0,0, "_1010",0, "_1011",0 = "_1100",0, "_1101",0, "_1110",0, "_1111",0 offset8 AND R0,R10,#255 ; Offset for LDF/STF/LDC/STC MOV R0,R0,LSL #2 B offset ; Uses common offset code shift TST R10,#16 ; Shifts and rotates MOVNE R2,#"R" ; Register or immediate? MOVNE R3,R10,LSR #8 ANDNE R3,R3,#15 MOVEQ R2,#"#" MOVEQ R3,R10,LSR #7 ANDEQS R3,R3,#31 MOVEQ R3,#32 ; If immediate and shift by 0, set to 32 MOV R1,R10,LSR #5 ; Get shift type ANDS R1,R1,#3 TEQEQ R2,#"#" TEQEQ R3,#32 BEQ decode ; If LSL #0 [LSL #32], ignore it TEQ R1,#3 TEQEQ R2,#"#" TEQEQ R3,#32 MOVEQ R1,#4 ; If ROR #0 [ROR #32], set to RRX ADR R0,shname ADD R0,R0,R1,LSL #2 ADD R0,R0,R1,LSL #1 BL copy ; Append shift name TEQ R1,#4 BEQ decode ; If RRX, don't append register or constant STRB R2,[R8],#1 MOV R0,R3 TEQ R2,#"R" BEQ regno_x ; If register, append register number MOV R1,R8 ; else append constant MOV R2,#9 SWI XOS_ConvertInteger4 MOV R8,R1 B decode shname = ",LSL ",0, ",LSR ",0, ",ASR ",0, ",ROR ",0, ",RRX",0 ALIGN numregs AND R0,R10,#1:SHL:15 MOV R0,R0,LSR #15 ; Number of registers for LFM/SFM AND R1,R10,#1:SHL:22 ORRS R0,R0,R1,LSR #21 MOVEQ R0,#4 ADD R0,R0,#"0" STRB R0,[R8],#1 B decode c_5to7 MOV R0,R10,LSR #5 ; Constant ANDS R0,R0,#7 MOVNE R1,#"," STRNEB R1,[R8],#1 BLNE regno B decode pc_offset12 MOV R0,R10,LSL #20 ; [PC,#offset] -> address, for LDR/STR MOV R0,R0,ASR #20 pc_offset TST R10,#1:SHL:23 SUBEQ R0,R11,R0 ADDNE R0,R11,R0 ADD R0,R0,#8 BIC R0,R0,#&FC000000 B address pc_offset8 MOV R0,R10,LSL #24 ; [PC,#offset] -> address, for copro MOV R0,R0,ASR #22 B pc_offset offsetis TEQ R6,#0 ; Append comment with offset as decimal BEQ decode ; if > 9 BL tab ; (this is because the offset code above ADRL R0,comment ; doesn't set this flag if offset < 10) BL copy MOV R0,R6 MOV R1,R8 MOV R2,#9 SWI XOS_ConvertInteger4 MOV R8,R1 B decode b_20to23 MOV R0,R10,LSR #20 ; Constant AND R0,R0,#15 B regno_x lflag TST R10,#1:SHL:22 ; "L" flag MOVNE R0,#"L" STRNEB R0,[R8],#1 B decode cache AND R0,R10,#&F00 ; Append comment for cache control TEQ R0,#&F00 ; (if copro 15) BNE decode MOV R2,R10,LSR #16 AND R2,R2,#15 BL tab LDR R0,flags TST R0,#flag_arm6 ; Test 'ARM6 or later' flag ADREQ R0,cache3x ADRNE R0,cache6x BL copy ADREQ R0,cache3 BEQ cachex TST R10,#1:SHL:20 ; MCR or MRC? ADREQ R0,cache6w ADRNE R0,cache6r cachex LDRB R2,[R0,R2] ADD R0,R0,R2 BL copy B decode cache3 = cache30-cache3,cache31-cache3,cache32-cache3,cache33-cache3 = cache34-cache3,cache35-cache3,cache3u-cache3,cache3u-cache3 = cache3u-cache3,cache3u-cache3,cache3u-cache3,cache3u-cache3 = cache3u-cache3,cache3u-cache3,cache3u-cache3,cache3u-cache3 cache6r = cache60r-cache6r,cache6u -cache6r,cache6u -cache6r,cache6u -cache6r = cache6u -cache6r,cache65r-cache6r,cache66r-cache6r,cache6u -cache6r = cache6u -cache6r,cache6u -cache6r,cache6u -cache6r,cache6u -cache6r = cache6u -cache6r,cache6u -cache6r,cache6u -cache6r,cache6u -cache6r cache6w = cache6u -cache6w,cache61w-cache6w,cache62w-cache6w,cache63w-cache6w = cache6u -cache6w,cache65w-cache6w,cache66w-cache6w,cache67w-cache6w = cache6u -cache6w,cache6u -cache6w,cache6u -cache6w,cache6u -cache6w = cache6u -cache6w,cache6u -cache6w,cache6u -cache6w,cache6u -cache6w cache3x = "; ARM3 ",0 cache30 cache60r = "ID",0 cache32 cache61w = "control",0 cache33 = "cacheable",0 cache34 = "updateable",0 cache35 = "disruptive",0 cache3u cache6u = "- bad reg",0 cache6x = "; ARM6 ",0 cache62w = "MMU base",0 cache63w = "domains",0 cache65r = "FSR",0 cache65w = "TLB flush ctrl",0 cache66r = "FAR",0 cache66w = "TLB purge ctrl",0 cache67w = "IDC " cache31 = "flush",0 ALIGN adr ADD R2,R11,#8 ; ADR address LDR R1,flags TST R1,#flag_useadrl ; If flag set, then MOVNE R1,#1 ; set up ADRL/ADRX flag for poss. ADRL MOVEQ R1,#0 adr_cmn STR R1,adrlx_f AND R0,R10,#255 ; Base address in R2 MOV R1,R10,LSR #7 ; Calculate the offset AND R1,R1,#30 TST R10,#1:SHL:22 ; then the referenced address ADDEQ R0,R2,R0,ROR R1 ; (for efficiency we do the rotate NOW!) SUBNE R0,R2,R0,ROR R1 BIC R0,R0,#&FC000000 ; mask for 26-bit value STR R0,adrlx B address ; Now append the address adrl LDR R3,prev ; ADRL/ADRX address LDR R2,adrlx ; Get ADR address LDR R1,adrlx_f ADD R1,R1,#1 ; Set up for poss. ADRX TEQ R1,#3 ; If already ADRX, set up for next ADR MOVEQ R1,#0 B adr_cmn ; Now sort out the extra offset lfm_sfm LDR R1,flags ; LFM and SFM - select display format TST R1,#flag_lfmstack + flag_lfs BEQ usefm ; If no special format selected, use standard TST R10,#1:SHL:20 ADRNE R9,mload ADREQ R9,mstore TST R1,#flag_lfs ; Try to use LFS/SFS if selected ADDNE R9,R9,#4 ; else try stack form of LFM/SFM MOV R0,R10,LSR #15 ; Get number of FP registers BIC R0,R0,#&7E ORR R0,R0,R0,LSR #6 ANDS R0,R0,#3 MOVEQ R0,#4 ADD R0,R0,R0,LSL #1 ; Multiply by 3 AND R2,R10,#255 ; Get the offset (div 4) AND R14,R10,#3:SHL:23 TEQ R14,#1:SHL:23 ; Post-indexed, +ve offset? IA form ADDEQ R9,R9,#1 BEQ fmpos TEQ R14,#2:SHL:23 ; Pre-indexed, -ve offset? DB form BNE usefm TST R10,#1:SHL:21 ; DB form: check writeback TEQEQ R2,#0 ; If clear, and offset = 0, use this BEQ usefmsm TEQ R2,R0 ; DB form: offset = num of regs? BNE usefm ; If not, use standard form B usefmsm ; else use selected form fmpos TEQ R2,#0 ; IA form: offset = 0? BICEQ R10,R10,#1:SHL:21 ; if so, no writeback required TEQNE R2,R0 ; IA form: offset = num of regs? BEQ usefmsm usefm TST R10,#1:SHL:24 ; Use standard form ADREQ R9,fmsmpos ADRNE R9,fmsmpre B decode usefmsm TST R1,#flag_stack ; Use selected form BEQ iadb ; 'Stack' option selected? AND R0,R10,#&F0000 ; If so, is R13 used? TEQ R0,#&D0000 ADDEQ R9,R9,#2 ; If so, use FD/EA form iadb ADR R0,iadb LDRB R9,[R9] ADD R9,R9,R0 B decode mload = fmdb-iadb, fmia-iadb, fmea-iadb, fmfd-iadb = fsdb-iadb, fsia-iadb, fsea-iadb, fsfd-iadb mstore = fmdb-iadb, fmia-iadb, fmfd-iadb, fmea-iadb = fsdb-iadb, fsia-iadb, fsfd-iadb, fsea-iadb fmsmpos = "M© F¬,À,[R³],#¢¾Ä",0 ; LFM/SFM normal fmsmpre = "M© F¬,À,[R³,#¢¾]¼Ä",0 ; LFM/SFM normal fmdb = "M©DB F¬,À,[R³]¼",0 fmia = "M©IA F¬,À,[R³]¼",0 fmea = "M©EA F¬,À,[R³]¼",0 fmfd = "M©FD F¬,À,[R³]¼",0 fsdb = "S©DB R³¼,{Ë}",0 fsia = "S©IA R³¼,{Ë}",0 fsea = "S©EA R³¼,{Ë}",0 fsfd = "S©FD R³¼,{Ë}",0 ALIGN lfs_sfs MOV R0,R10,LSR #15 ; Get number of FP registers BIC R0,R0,#&7E ORR R0,R0,R0,LSR #6 ANDS R0,R0,#3 MOVEQ R0,#4 SUBS R0,R0,#1 MOV R1,R10,LSR #12 MOV R2,#"F" STRB R2,[R8],#1 AND R1,R1,#7 ADD R1,R1,#"0" STRB R1,[R8],#1 BEQ decode ADD R1,R1,R0 BIC R1,R1,#8 TEQ R0,#1 MOVEQ R0,#"," MOVNE R0,#"-" STRB R0,[R8],#1 STRB R2,[R8],#1 STRB R1,[R8],#1 B decode arith ADR R0,arithlist arith_test MOV R1,R10,LSR #21 AND R1,R1,#7 arith_test_fp ADD R0,R0,R1,LSL #2 B copy_x arithlist = "AND",0,"EOR",0,"SUB",0,"RSB",0,"ADD",0,"ADC",0,"SBC",0,"RSC",0 test ADR R0,testlist B arith_test testlist = "TST",0,"TEQ",0,"CMP",0,"CMN",0,"ORR",0,"MOV",0,"BIC",0,"MVN",0 fparith ADR R0,fparithlist MOV R1,R10,LSR #20 AND R1,R1,#15 B arith_test_fp fparithlist = "ADF",0,"MUF",0,"SUF",0,"RSF",0,"DVF",0,"RDF",0,"POW",0,"RPW",0 = "RMF",0,"FML",0,"FDV",0,"FRD",0,"POL",0,"F0D",0,"F0E",0,"F0F",0 fparithunary ADR R0,fparithunarylist MOV R1,R10,LSR #20 AND R1,R1,#15 B arith_test_fp fparithunarylist = "MVF",0,"MNF",0,"ABS",0,"RND",0,"SQT",0,"LOG",0,"LGN",0,"EXP",0 = "SIN",0,"COS",0,"TAN",0,"ASN",0,"ACS",0,"ATN",0,"URD",0,"NRM",0 fptrans ADR R0,fptranslist MOV R1,R10,LSR #20 AND R1,R1,#15 SUB R1,R1,#2 CMP R1,#4 BLT arith_test_fp ADR R0,fptransundef BL copy CMP R1,#8 ADDLT R1,R1,#"2" ADDGE R1,R1,#"C"-10 STRB R1,[R8],#1 B decode fptranslist = "WFS",0,"RFS",0,"WFC",0,"RFC",0 fptransundef = "FT",0,0 mull ADR R0,mulllist MOV R1,R10,LSR #21 AND R1,R1,#3 ADD R0,R0,R1 B arith_test_fp mulllist = "UMUL",0,"UMLA",0,"SMUL",0,"SMLA",0 fpcompare MOV R0,#"C" STRB R0,[R8],#1 TST R10,#1:SHL:21 MOVEQ R0,#"M" MOVNE R0,#"N" STRB R0,[R8],#1 MOV R0,#"F" STRB R0,[R8],#1 TST R10,#1:SHL:22 MOVNE R0,#"E" STRNEB R0,[R8],#1 B decode char AND R0,R10,#&FF B vdu_com r12offset LDR R0,flags TST R0,#flag_useadrw BEQ notr12 AND R0,R10,#&0FF00000 TEQ R0,#&02400000 TEQNE R0,#&02800000 ANDNE R0,R10,#&0C000000 TEQNE R0,#&04000000 ANDEQ R0,R10,#&F000 TEQEQ R0,#&C000 ; No W form if R12 is destination register BEQ notr12 B decode notr12 SUB R2,R2,#10 ADD R9,R9,R2 B find adrwoff AND R0,R10,#&FF AND R1,R10,#&F00 MOV R1,R1,LSR #7 MOV R0,R0,ROR R1 B address ldrwoff MOV R0,R10,LSL #20 MOV R0,R0,LSR #20 B address mul_check AND R0,R10,#&F ; Check for silly thing like MUL Rx,Rx,Ry AND R1,R10,#&F0000 ; or MUL R15,Rx,Ry TEQ R0,R1,LSR #16 TEQNE R1,#&F0000 BLEQ tab ADREQ R0,rdisrm ; Append comment if found BLEQ copy B decode rdisrm = "; *** Rd=Rm or Rd=PC",0 ALIGN minus TST R10,#1:SHL:23 ; Negative offset? MOVEQ R0,#"-" STREQB R0,[R8],#1 B decode arm250orlater ADR R2,arm250 B armxorlater arm3orlater ADR R2,arm3 B armxorlater arm6orlater ADR R2,arm6 B armxorlater arm7orlater ADR R2,arm7 armxorlater BL tab ; Append comment "ARMxxx or later" ADR R0,arm BL copy MOV R0,R2 BL copy ADR R0,orlater B copy_x arm = "; ARM",0 arm250 = "250",0 arm3 = "3",0 arm6 = "6",0 arm7 = "7",0 orlater = " and later",0 ALIGN ; This is the instruction templates list. ; The order in which the tokens appear is important, since the list is ; scanned sequentially. ; Format is: ; +0 AND mask ; +4 TEQ value (instruction AND mask == value) ; +8 Offset to next token (from one AND mask to the next) ; +9 Template string, null terminated ; Nulls appended to ensure word alignment ; If offset to next token = 0, then this is the list terminator, not a token withvdu Token FFFFF00,F000100,"VDU© Ö" Token FFFFF00,F020100,"VDU©X Ö" instructions Token FE000F0,0000090,"MUL©¸ R³,Rº,R§¡" Token FE000F0,0200090,"MLA©¸ R³,Rº,R§,Rª¡" Token FB000F0,1000090,"SWP©¨ Rª,Rº,[R³]Ó" Token F8000F0,0800090,"Ò©¸ Rª,R³,Rº,R§Õ" Token E0000F0,0000090,"" Token E0000F0,00000B0,"" Token E0000F0,00000D0,"" Token E0000F0,00000F0,"" Token E000010,6000010,"" Token FB0F000,120F000,"MSR© ·½,RºÔ" Token FB6F000,320F000,"MSR© ·½,#¯Ô" Token FBF0000,10F0000,"MRS© Rª,·Ô" Token FFF0000,24C0000,"×ADR©W Rª,-&Ø" Token FFF0000,28C0000,"×ADR©W Rª,&Ø" Token FFF0000,24F0000,"ADR© Rª,&È" Token FFF0000,28F0000,"ADR© Rª,&È" Token F000000,0000000,"Ì©¸ Rª,R³,Rº¿" Token F000000,2000000,"Ì©¸ Rª,R³,#¯" Token F900000,1100000,"Í©µ R³,Rº¿" Token F900000,3100000,"Í©µ R³,#¯" Token FA00000,1800000,"Í©¸ Rª,R³,Rº¿" Token FA00000,3800000,"Í©¸ Rª,R³,#¯" Token FA00000,1A00000,"Í©¸ Rª,Rº¿" Token FA00000,3A00000,"Í©¸ Rª,#¯" Token F2F0000,50C0000,"×£R©¨W Rª,¢&Ù" Token F000000,4000000,"£R©¨¹ Rª,[R³],#¢´Ä" Token F2F0000,50F0000,"£R©¨¹ Rª,&Â" Token F000000,5000000,"£R©¨ Rª,[R³,#¢´]¼Ä" Token F000000,6000000,"£R©¨¹ Rª,[R³],¢Rº¿Ä" Token F000000,7000000,"£R©¨ Rª,[R³,¢Rº¿]¼Ä" Token E000000,8000000,"£M©± R³¼,{²}¤" Token F000000,A000000,"B© &°" Token F000000,B000000,"BL© &°" Token F000000,F000000,"SWI© ¶" Token F200000,C000000,"" Token F200F00,C200100,"£F©« F¬,[R³],#¢¾Ä" Token F2F0F00,D0F0100,"£F©« F¬,&Ã" Token F000F00,D000100,"£F©« F¬,[R³,#¢¾]¼Ä" Token F3F0F00,C0F0200,"SFM© F¬,À,&Ã" Token E100F00,C000200,"SFÊ" Token F3F0F00,D1F0200,"LFM© F¬,À,&Ã" Token E100F00,C100200,"LFÊ" Token F008F10,E000100,"Î©«» F¬,F,®" Token F008F10,E008100,"Ï©«» F¬,®" Token F90FF10,E90F110,"Ñ© F,®" Token FF00F10,E000110,"FLT©« F¥,Rª" Token FF00F10,E100110,"FIX« Rª,®" Token F000F10,E000110,"Ð© Rª" Token F000010,E000000,"CDP© CP§,Å,Cª,C³,CºÁ" Token F100010,E000010,"MCR© CP§,¦,Rª,C³,CºÁÇ" Token F100010,E100010,"MRC© CP§,¦,Rª,C³,CºÁÇ" Token F000000,C000000,"£C©¹Æ CP§,Cª,[R³],#¢¾Ä" Token F2F0000,D0F0000,"£C©Æ CP§,Cª,&Ã" Token F000000,D000000,"£C©Æ CP§,Cª,[R³,#¢¾]¼Ä" & 0,0,0 memoryflags MOV R1,#1 memoryflags1 STMFD R13!,{R1-R12,R14} LDR R12,[R12] MOV R10,R1 MOV R1,R0 ADR R0,args ADR R2,buffer MOV R3,#256-buffptr SWI XOS_ReadArgs LDMVSFD R13!,{R1-R12,PC} TEQ R3,#256-buffptr-4*flag__b TEQEQ R10,#1 BEQ current MOV R2,#1:SHL:(flag__b-1) LDR R3,flags ADR R4,buffer+4*flag__b flagbit LDR R0,[R4,#-4]! BL yesno LDMVSFD R13!,{R1-R12,PC} MOVS R2,R2,LSR #1 BNE flagbit STR R3,flags LDMFD R13!,{R1-R12,PC}^ notyn_err & 220 = "Bad switch state",0 args = "fdwithr13=fd=f," = "apcs=a," = "lfmstack=sfmstack=lfm=sfm=m," = "lfs=sfs=s," = "quoteswis=quote=swi=q," = "usedcd=dcd=d," = "usevdu=vdu=v," = "andeqasdcd=andeq=nop=n," = "useadrl=adrl=l," = "useadrw=adrw=w",0 ALIGN yesno TEQ R0,#0 MOVEQS PC,R14 LDRB R1,[R0,#1] TEQ R1,#0 BNE notyn LDRB R1,[R0] TEQ R1,#"0" TEQNE R1,#"N" TEQNE R1,#"n" BICEQ R3,R3,R2 MOVEQS PC,R14 TEQ R1,#"1" TEQNE R1,#"Y" TEQNE R1,#"y" ORREQ R3,R3,R2 MOVEQS PC,R14 notyn ADR R0,notyn_err ORRS PC,R14,#1:SHL:28 current LDR R8,flags ADR R0,flagtext MOV R7,#1 showflag LDRB R1,[R0] TEQ R1,#0 LDMEQFD R13!,{R1-R12,PC}^ SWI XOS_Write0 LDMVSFD R13!,{R1-R12,PC} TST R8,R7 BL printyesno MOVVC R7,R7,LSL #1 BVC showflag LDMFD R13!,{R1-R12,PC} printyesno STMFD R13!,{R0,R14} ADREQ R0,printno ADRNE R0,printyes SWI XOS_Write0 SWIVC XOS_NewLine LDMFD R13!,{R0,PC} printyes = " Yes",0 printno = " No",0 flagtext = " Use FD with R13 :",0 = " Use APCS names :",0 = " LFM/SFM stack where possible :",0 = "LFS/SFS for LFM/SFM where possible :",0 = " Put quotes around SWI names :",0 = "Use DCD for undefined instructions :",0 = " Use VDU instead of SWI OS_WriteI :",0 = "Use DCD instead of ANDEQ & similar :",0 = " Use ADRL/X for ADR + ADD/SUBs :",0 = " Use ADRW/LDRW for R12±m/[R12,#m] :",0 = 0 END