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Text File | 1993-03-07 | 61.2 KB | 1,384 lines

%ltorg Usage: ltorg Summary: Tells the assembler that it is okey to place literals at this position. An ltorg is inserted at the end of all areas but it can be necessary to insert ltorgs at other positions in the file as there must not be more than 4095 bytes between any use of a litarate load (e.g., ldr r0,=31415) and the closest literate area. %lnk Usage: lnk filename Summary: The assembler switches input to the given file. The rest of the current file is ignored. %get Usage: get filename Summary: The assembler switches input to the new file, and returns to the old file afterwords. The result is as if the new file was textually inserted at the position of get. %rn Usage: <Identifier> rn <Expression> Summary: The identifier can now be used as a cpu register in future instructions. The expression must be in the interval 0 to 15 inclusive. %fn Usage: <Identifier> rn <Expression> Summary: The identifier can now be used as a fpu register in future instructions. The expression must be in the interval 0 to 7 inclusive %cn Usage: <Identifier> rn <Expression> Summary: The identifier can now be used as a coprocessor register in future instructions. The expression must be in the interval 0 to 15 inclusive. %equ Usage: <Identifier> equ <Expression> Summary: Defines an numerical identifier. '*' is a short form of equ. %* Usage: <Identifier> * <Expression> Summary: Defines an numerical identifier. '*' is a short form of equ. %dcb Usage: dcb <Expression> {,<Expression>}* Summary: Dcb defines one or more bytes. String constants are allowed as expressions, which causes the characters of the string to be loaded in consecutive bytes. '=' is a short form of dcb. %= Usage: = <Expression> {,<Expression>}* Summary: '=' defines one or more bytes. String constants are allowed as expressions, which causes the characters of the string to be loaded in consecutive bytes. '=' is a short form of dcb. (See ldr and str for alternative use of '='.) %dcw Usage: dcw <Expression> {,<Expression>}* Summary: Dcw defines one or more 16-bits word. String constants can not contain more than two characters and are converted to 16-bits integers, 1:st character + (2:nd character << 8). %dcd Usage: dcd <Expression> {,<Expression>}* Summary: Dcw defines one or more 32-bits word. String constants can not contain more than four characters and are converted to 32-bits integers, 1:st character + (2:nd character << 8) + (3:rd character << 16) + (4:th character << 24). '&' is a short form of dcd. %& Usage: & <Expression> {,<Expression>}* Summary: '&' defines one or more 32-bits word. String constants can not contain more than four characters and are converted to 32-bits integers, 1:st character + (2:nd character << 8) + (3:rd character << 16) + (4:th character << 24). '&' is a short form of dcd. %dcfs Usage: dcfs <FloatExpression> {,<FloatExpression>}* Summary: Dcfs defines one or more 32-bits floats. %dcfd Usage: dcfd <FloatExpression> {,<FloatExpression>}* Summary: Dcfd defines one or more 64-bits floats. %dcfe Usage: dcfe <FloatExpression> {,<FloatExpression>}* Summary: Dcfe defines one or more 96-bits floats. Note: Dcfe is not implemented! %dcfp Usage: dcfp <FloatExpression> {,<FloatExpression>}* Summary: Dcfp defines one or more 96-bits packed decimal floats. Note: Dcfp is not implemented! %area Usage: area <Identifier> {,Attributes}* Summary: Area selects a new area for storage. If the identifier is new then a new area will be defined with the selected attributes. It is not necessary to give the attributes if an old area is reselected. Currently implemented attributes are: CODE This area is for code, this is only for the linker. DATA This area is for data, this is only for the linker. NOINIT This area is for zero initsialized data. The assembler will check that this is true. READONLY This area is read only, this is only for the linker. %CODE Usage: area <Identifier> , CODE {,<Attributes>}* Summary: This tells the linker that this area contains code. Other attributes are DATA,NOINIT and READONLY. %DATA Usage: area <Identifier> , DATA {,<Attributes>}* Summary: This tells the linker that this area contains data. Other attributes are CODE,NOINIT and READONLY. %NOINIT Usage: area <Identifier> , NOINIT {,<Attributes>}* Summary: This tells the linker that this area contains zero initsialized data. The assembler will check that this is true. Other attributes are CODE,DATA and READONLY. %READONLY Usage: area <Identifier> , READONLY {,<Attributes>}* Summary: This tells the linker that this area is read only. Other attributes are CODE,DATA and NOINIT. %align Usage: align <Expression> Summary: Align moves the next item in the current area to an address which is an even multiplier of the expression. Note that the linker does not support bigger alignment than four. Note: The pad bytes are NOT set to zero! No default value exist as in Acorn's assembler and it is not possible to give an offset. %% Usage: % <Expression> Summary: '%' reserves the given numbers of bytes in the current area. Note: The bytes are NOT set to zero! %entry Usage: entry Summary: This is the entry point for the finished program. %^ Usage: ^ <Expression> Summary: '^' sets the storage counter used in '#' for laying out areas. Note: It is not possible to create register relative addresses as in Acorn's assembler. %# Usage: <Identifier> # <Expression> Summary: '#' sets the identifier equal to the storage counter, and then increments the counter with the expression. The expression must be positive. %{VAR} Usage: Don't, use @ instead. Summary: This is a synonym for @ in Acorn's assembler it is not availible in this assembler. %{PC} Usage: Don't, use . instead. Summary: This is a synonym for . in Acorn's assembler it is not availible in this assembler. %. E.g: CurrentPosition * . ; Gets the current position in the current area Summary: ',' returns the current position in the current area. %@ E.g: FillArea # 10-@ ; Makes the storage counter equal to 10, ; or gives an error if it already is larger. Summary: '@' returns the current value of the storage counter. %globl Usage: globl <Identifier> Summary: Globl instructs the assembler, and the linker, to keep this symbol in the object file. Globl is also used to introduce an identifier which is defined in another assembler file. The later usage is not compulsary as the assembler treats all undefined identifier as introduced by globl. This behaviour may however change. Note: Globl will probably be removed in future versions, use export, if the identifier is defined in this assembler file, and import if it is not. %export Usage: export <Identifier> Summary: Export instructs the assembler, and the linker, to keep this symbol in the object file. %import Usage: import <Identifier> Summary: Import is used to introduce an identifier which is defined in another assembler file. It is not compulsary as the assembler treats all undefined identifier as if they where imported. But it is nice for people who read the code, and the assembler may demand it in future versions. %Cond Usage: Don't Summary: This is only a short description of the condition codes. All instructons can take a condition code. the condition code is written directly after the mnemonic and before options, if it is present, e.g.: addeq add if equal. orrgts or if greater than, and update flags. bcs branch if carry set. ldmneib load multiple, with increment before, if not equal. The instruction will be executed if the conition is true. The possible conditions are: and they are true if: al Always, always. nv Never, never, this condition code should not be used! Use mov r0,r0 if a no-operation is needed. eq Equal, Z is set. ne Not Equal, Z is cleared. vs Overflow, V is set. vc No overflow, V is cleared. mi Minus, N is set. pl Plus, N is cleared. cs Carry set, C is set. cc Carry clear, C is cleared. hi Higher, C is set and Z is cleared. ls Lower or same, C is cleared or Z is set. ge Greater or equal, N is cleared and V is cleared, or N is set and V is set. lt Less, N is set and V is cleared, or N is cleared and V is set. gt Greater, 'ge' is true and Z is cleared. le Less or equal, 'lt' is true or Z is set. hs Higher or same, 'cs' is true. lo Lower 'cc' is true. If no condition is given then 'al' (Always) is assumed. %ShiftOp Usage: Don't Summary: This is only a short description of the possible shift operations. It is sometimes possible to shift the right operand in an instruction. The shift amount is a 5 bit constant or, in some instructions, the contents of the lowest byte in a register. E.g.: r0,lsl #1 shift r0 left one step. r2,ror r1 rotate r2 right the number of step given in lowest byte in r1. r3,rrx rotate r3, extended with the carry, right one step. Possible shifts are: Number of steps (if constant): lsl Logical shift left 0 to 31 lsr Logical shift right 0 to 32 asl Atitmetic shift left 0 to 32 asr Aritmetic shift right 0 to 32 ror Rotate rigth 0 to 31 rrx Rotate right extended Always 1 step. For a description of how the shift is done see the shift operation in question. %lsl E.g.: adds r1,r2,r3,lsl #2 ; r1 = r2+r3<<2 = r2+r3*4 Summary: Lsl shifts a register left inserting zeroes at the right end: C<--bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb<--0 The last bit moved out from the register is inserted in the carry if the main instruction does not affect the carry and the s-option is given, e.g., the lsl in the example will not set the carry as add sets the carry itself. The number of steps can be from 0 to 31 inclusive. It is sometimes possible to shift by the context of a register: adds r1,r2,r3,lsl r4 Only the eigth lowest bits in the register are used allowing shifts of up to 255 steps. Note: Lsl is identical to asl. %lsr E.g.: adds r1,r2,r3,lsr #2 ; r1 = r2+r3>>2 = r2+r3/4 (if r3 is unsigned) Summary: Lsr shifts a register right inserting zeroes at the left end: 0-->bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb-->C The last bit moved out from the register is inserted in the carry if the main instruction does not affect the carry and the s-option is given, e.g., the lsr in the example will not set the carry as add sets the carry itself. The number of steps can be from 0 to 32 inclusive. It is sometimes possible to shift by the context of a register: adds r1,r2,r3,lsr r4 Only the eigth lowest bits in the register are used allowing shifts of up to 255 steps. %asl E.g.: adds r1,r2,r3,lsl #2 ; r1 = r2+r3<<2 = r2+r3*4 Summary: Asl shifts a register left inserting zeroes at the right end: C<--bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb<--0 The last bit moved out from the register is inserted in the carry if the main instruction does not affect the carry and the s-option is given, e.g., the asl in the example will not set the carry as add sets the carry itself. The number of steps can be from 0 to 32 inclusive. It is sometimes possible to shift by the context of a register: adds r1,r2,r3,asl r4 Only the eigth lowest bits in the register are used allowing shifts of up to 255 steps. Note: Asl is identical to lsl. %asr E.g.: adds r1,r2,r3,asr #2 ; r1 = r2+r3>>>2 Summary: Asr shifts a register right inserting copies of the highest bit at the left end, i.e., the n most significants bits becomes equal to bit 31: /--\ \->bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb--->C The last bit moved out from the register is inserted in the carry if the main instruction does not affect the carry and the s-option is given, e.g., the asr in the example will not set the carry as add sets the carry itself. The number of steps can be from 0 to 32 inclusive. It is sometimes possible to shift by the context of a register: adds r1,r2,r3,asr r4 Only the eigth lowest bits in the register are used allowing shifts of up to 255 steps. %ror E.g.: adds r1,r2,r3,ror #2 Summary: Ror rotates the register right: /-----------------------------------\ \->bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb--->C The last bit moved out from the register is inserted in the carry if the main instruction does not affect the carry andthe s-option is given, e.g., the ror in the example will not set the carry as add sets the carry itself. The number of steps can be from 0 to 31 inclusive. It is sometimes possible to rotate by the context of a register: adds r1,r2,r3,ror r4 Only the eigth lowest bits in the register are used allowing rotates of up to 255 steps. %rrx E.g.: adds r1,r2,r3,rrx Summary: Rr rotates the register extended by the carry one step right: /-----------------------------------------\ \->bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb--->C--/ The lowest bit is inserted in the carry if the main instruction does not affect the carry and the s-option is given, e.g., the rrx in the example will not set the carry as add sets the carry itself. %Core3Op Usage: Don't Summary: This is only a short description of some cpu instructions. Syntax: <Core3Op><Cond><Sflag> <Dst>,<Lhs>,<Rhs> where <Core3Op> is one of: which can update the following flags: add <Dst> = <Lhs> + <Rhs> NCVZ adc <Dst> = <Lhs> + <Rhs> + C NCVZ sub <Dst> = <Lhs> - <Rhs> NCVZ sbc <Dst> = <Lhs> - <Rhs> - ~C NCVZ rsb <Dst> = <Rhs> - <Lhs> NCVZ rsc <Dst> = <Rhs> - <Lhs> - ~C NCVZ eor <Dst> = <Lhs> ^ <Rhs> NZ and <Rhs> can update C orr <Dst> = <Lhs> | <Rhs> NZ and <Rhs> can update C and <Dst> = <Lhs> & <Rhs> NZ and <Rhs> can update C bic <Dst> = <Lhs> & ~<Rhs> NZ and <Rhs> can update C <Cond> see Cond. <Sflag> is one of: s Flags are updated according to the result. (empty) No flag is updated. <Dst> and <Lhs> are registers, (identifiers defined with 'rn'). <Rhs> is one of: #<Expression> An integer which is possible to express as an 8 bit value rotated an even numbers of bits. The assembler will change the mnemonic, if necessary, to achieve this. Mnemonics that are changed are add/sub, adc/sbc and and/bic. Register Register,rrx see rrx Register,<ShiftOp> #<Expression> see ShiftOp Register,<ShiftOp> Register see ShiftOp %CoreCmp Usage: Don't Summary: This is only a short description of some cpu instructions. Syntax: <CoreCmp><Cond><Sflag><Pflag> <Lhs>,<Rhs> where <CoreCmp> is one of: which updates the following flags: cmp <Lhs> - <Rhs> NCVZ cmn <Lhs> + <Rhs> NCVZ tst <Lhs> & <Rhs> NZ and <Rhs> can update C teq <Lhs> ^ <Rhs> NZ and <Rhs> can update C <Cond> see Cond. <Sflag> is not used, flags are always uppdated according to the result. An 's' can be given but it is ignored. <Pflag> is one of: p The result of the operation is moved to the PSR, i.e., the NCVZ flags are set from the top four bits of the result. In modes other than the user mode the NCVZIF flags are set from the top six bits and the mode bits are set from the two lowest bits. (empty) The flags are updated according to the result of the operation <Dst> and <Lhs> are registers, (identifiers defined with 'rn'). <Rhs> is one of: #<Expression> An integer which is possible to express as an 8 bit value rotated an even numbers of bits. The assembler will change the mnemonic, if necessary, to achieve this. Mnemonics that are changed are cmp/cmn. Register Register,rrx see rrx Register,<ShiftOp> #<Expression> see ShiftOp Register,<ShiftOp> Register see ShiftOp %add E.g.: add r0,r1,r2 Summary: Add. See: Core3Op %adc E.g.: adc r0,r1,r2 Summary: Add with carry. See: Core3Op %syb E.g.: sub r0,r1,r2 Summary: Subtract. See: Core3Op %sbc E.g.: sbc r0,r1,r2 Summary: Subtract with carry. See: Core3Op %rsb E.g.: rsb r0,r1,r2 Summary: Reverse subtract. See: Core3Op %rsc E.g.: rsc r0,r1,r2 Summary: Reverse subtract with carry. See: Core3Op %eor E.g.: eor r0,r1,r2 Summary: Bitwise exclusive or. See: Core3Op %orr E.g.: orr r0,r1,r2 Summary: Bitwise or. Acorn choosed this spelling! See: Core3Op %and E.g.: and r0,r1,r2 Summary: Bitwise and. See: Core3Op %bic E.g.: bic r0,r1,r2 Summary: Bit clear, this is an and where the right operand is inverted. See: Core3Op %mvn E.g.: mvn r0,r1 Summary: Move not, i.e., the source operand is inverted. Syntax: mvn<Cond><Sflag> <Dst>,<Rhs> Mvn updates the N and Z flags if the Sflag is given, <Rhs> can update the carry. <Cond> see Cond. <Sflag> is one of: s Flags are updated according to the result. (empty) No flag is updated. <Dst> is a register, (identifiers defined with 'rn'). <Rhs> is one of: #<Expression> An integer which is possible to express as an 8 bit value rotated an even numbers of bits. The assembler will change the mnemonic, if necessary, to a mov to achieve this. Register Register,rrx see rrx Register,<ShiftOp> #<Expression> see ShiftOp Register,<ShiftOp> Register see ShiftOp %mov E.g.: mov r0,r1 Summary: Move, can also be used for shifts (,if you can not integrate the shift in another instruction): mov r0,r1,lsl #2 Syntax: mov<Cond><Sflag> <Dst>,<Rhs> Mov updates the N and Z flags if the Sflag is given, <Rhs> can update the carry. <Cond> see Cond. <Sflag> is one of: s Flags are updated according to the result. (empty) No flag is updated. <Dst> is a register, (identifiers defined with 'rn'). <Rhs> is one of: #<Expression> An integer which is possible to express as an 8 bit value rotated an even numbers of bits. The assembler will change the mnemonic, if necessary, to a mvn to achieve this. Register Register,rrx see rrx Register,<ShiftOp> #<Expression> see ShiftOp Register,<ShiftOp> Register see ShiftOp %tst E.g.: tst r0,r1 Summary: Test, a bitwise and where the result isn't saved. See: CoreCmp %teq E.g.: teq r0,r1 Summary: Test if equal, a bitwise exclusive or where the result isn't saved. See: CoreCmp %cmp E.g.: cmp r0,r1 Summary: Compare, a subtraction where the result isn't saved. See: CoreCmp %cmn E.g.: cmn r0,r1 Summary: Compare negated, i.e., the second operand is negated before comparasion. Cmn is an addition where the result isn't saved. See: CoreCmp %mul E.g.: mul r0,r1,r2 Summary: Integer multiplication. The destination and the left operand must be different, the assembler will change the order of the operands to achieve this. Syntax: mul<Cond><Sflag> <Dst>,<Lhs>,<Rhs> <Cond> see Cond. <Sflag> is one of: s The NZ flags are updated according to the result, and the carry is undefined. (empty) No flag is updated. <Dst>,<Lhs> and <Rhs> are registers, (identifiers defined with 'rn'). %mla E.g.: mla r0,r1,r2,r4 ; r0 = r1*r2+r4 Summary: Integer multiplication with accumulator. The destination and the left operand of the multiplication must be different, the assembler will change the order of the operands to achieve this. Syntax: mla<Cond><Sflag> <Dst>,<Lhs>,<Rhs>,Acc <Cond> see Cond. <Sflag> is one of: s The NZ flags are updated according to the result, and the carry is undefined. (empty) No flag is updated. <Dst>,<Lhs>,<Rhs> and <Acc> are registers, (identifiers defined with 'rn'). %b E.g.: beq label10 Summary: This is the branch instruction. Syntax: b<Cond> <Destination> b<Cond> #<Expression> <Cond> see Cond. <Destination> The assembler will calculate the offset to the destination and take care of prefetch if no '#' is given. <Expression> The expression is treated as the byte offset that should be added to the pc. Only even multiples of four are allowed. Undefined identifiers are allowed in both forms. %bl E.g.: bl label10 Summary: This is the branch with link instruction. The address of the next instruction is saved in cpu register 14, and the execution continues at the given destiniation. Syntax: bl<Cond> <Destination> bl<Cond> #<Expression> <Cond> see Cond. <Destination> The assembler will calculate the offset to the destination and take care of prefetch if no '#' is given. <Expression> The expression is treated as the byte offset that should be added to the pc. Only even multiples of four are allowed. Undefined identifiers are allowed in both forms. %swi E.g.: swi 256+'a' Summary: Software interrupt. The address of the next instruction is saved in cpu register svc-14, and the execution continues at 0x00000008 with the I flag set and the svc mode selected. This instruction is used for system calls. Syntax: swi<Cond> <Expression> <Cond> see Cond. the expression can be any 24-bit integer. %swp E.g.: swpb r0,r1,[r2] Summary: Swap is used to implement looks on multi processor computers. Syntax: swp<Cond><Bflag> <Dst>,<Src>,[<Addr>] <Cond> see Cond. <Bflag> b This is a byte operation. The value is zero extended. (empty) This is a 32-bits operation. <Dst>,<Src> and <Addr> are registers, (identifiers defined with 'rn'). The semantic is: mov <temp>,<Src> ldr<Cond><Bflag> <Dst>, [<Addr>] str<Cond><Bflag> <temp>,[<Addr>] with a lock signal set on the buss so that other cpus can detect that an atomic operation is under progress. Note: Not availible on ARM2. %adr: E.g.: adr r0,CloseLabel Summary: This is a syntesized instruction which is used to put the address of a label into a register. The assembler generates either: add r0,pc,#Offset or sub r0,pc,#Offset depending on the relative position of the instruction and the label. Syntax: add<Cond> <Dst>,<Position> <Cond> see Cond. <Position> is a label in the same area as the instruction. The range is limited to the positions that can be generated by adding/subtracting an 8-bits value rotated by an even number of steps to/from the pc. %ldm: E.g.: ldm sp!,{r0-r4,pc} Summary: This instruction loads multiple registers. It is normaly used to pop from stacks, but is also useful for copying memory. Syntax: ldm<Cond><Direction> <Addr><!flag>,<RegisterList><^flag> <Cond> see Cond. <Direction> is one of: ib increment <Addr>, before first load. ia increment <Addr>, after first load. db decrement <Addr>, before first load. da decrement <Addr>, after first load. fd use a full descending stack, same as ia. ed use an empty descending stack, same as ib. fa use a full ascending stack, same as da. ea use an empty ascending stack, same as db. <Addr> is a register, (identifiers defined with 'rn'). <!flag> ! <Addr> = <Addr> + 4*number of registers, if increment, = <Addr> - 4*number of registers, if decrement. (empty) Do not change <Addr> <RegisterList> is a comma separated list of registers inside braces or a '#' followed by a 16-bits integer expression. <^flag> ^ If pc is loaded then the CZNV will be updated. If the cpu is in a non-user mode then the CZNVIF and the mode bits will be updated. If a non-user mode is selected and the pc is not loaded then the '^' means that it is the user registers that are loaded. (empty) Only the address part of the pc is updated. %stm: E.g.: stm sp!,{r0-r4,pc} Summary: This instruction stores multiple registers. It is normaly used to push on stacks, but is also useful for copying memory. Syntax: stm<Cond><Direction> <Addr><!flag>,<RegisterList><^flag> <Cond> see Cond. <Direction> is one of: ib increment <Addr>, before first store. ia increment <Addr>, after first store. db decrement <Addr>, before first store. da decrement <Addr>, after first store. fd use a full descending stack, same as db. ed use an empty descending stack, same as da. fa use a full ascending stack, same as ib. ea use an empty ascending stack, same as ia. <Addr> is a register, (identifiers defined with 'rn'). <!flag> ! <Addr> = <Addr> + 4*number of registers, if increment, = <Addr> - 4*number of registers, if decrement. (empty) Do not change <Addr> <RegisterList> is a comma separated list of registers inside braces or a '#' followed by a 16-bits integer expression. <^flag> ^ No meaning in user mode, but in non-user mode means that it is the user registers that are stored. (empty) Use the current modes register. %ldr E.g.: ldr r0,[r1,r2,lsl #2] ; Loads the r2'th word from the table at r1 into r0. Summary: The load instruction has many possibilities so the following description might be a bit complicated. Syntax: ldr<Cond><Bflag><Tflag> <Dst>,<Address><!flag> <Cond> see Cond. <Bflag> b This is a byte operation. The value is zero extended. (empty) This is a 32-bits operation, the value read is rotated so that the byte pointed at ends up in the low byte of <Dst>. <Tflag> t Make a user mode bus cycle even if in a non-user mode. This flag is only allowed if the address is a post inc/decrement. (empty) Use the bus cycle for the current mode. <Dst> is a register, (identifiers defined with 'rn'). <Address> The <Tflag> is allowed in 1 to 5 but not in the others. The <!flag> is allowed in 6 to 9 but not in the others. 10 and 11 is syntetic sugare for pc relative addressing. 1 [ <Addr> ] indirect register. 2 [ <Addr> ],#<Offset> indirect register with immediate post inc/decrement. 3 [ <Addr> ],<+/-> <RegOffset> 4 [ <Addr> ],<+/-> <RegOffset>, rrx 5 [ <Addr> ],<+/-> <RegOffset>,<ShiftOp> #<Expression> indirect register with register post inc/decrement. 6 [ <Addr>,#<Offset> ] indirect register with immediate pre inc/decrement. 7 [ <Addr>,<+/-> <RegOffset> ] 8 [ <Addr>,<+/-> <RegOffset>, rrx ] 9 [ <Addr>,<+/-> <regOffset>, <ShiftOp> #<Expression> ] indirect register with register pre inc/decrement. 10 <Expr> Translated into [pc,#<Offset>] where <Expr> = pc+<Offset> compensated for prefetching. 11 =<Expr> Translated into a [pc,#<Offset>] pointing at a word in a literal area (see ltorg) containing <Expr>. The assembler tries to share constants if possible. <Addr> and <RegOffset> are registers, (identifiers defined with 'rn'). <+/-> a plus or minus sign, or nothing which means plus. <Offset> is an expression which value fits in a 12-bit constant with a sign bit ,-4095 to +4095 inclusive. rrx see rrx. <ShiftOp> see ShiftOp. <!flag> ! <Addr> = <Addr> <+/-> Offset This flag is only allowed if the address is a pre inc/decrement. The <Addr> register is always updated if the <Address> is a post inc/decrement. (empty) Do not update the <Addr> register unless the <Address> is a post inc/decrement. %str E.g.: str r0,[r1,r2,lsl #2] ; Store r0 at the r2'th word in the table at r1. Summary: The store instruction has many possibilities so the following description might be a bit complicated. Syntax: str<Cond><Bflag><Tflag> <Src>,<Address><!flag> <Cond> see Cond. <Bflag> b This is a byte operation. The top 24-bits in <Src> are ignored. (empty) This is a 32-bits operation, the two lowes bits of the address are ignored. <Tflag> t Make a user mode bus cycle even if in a non-user mode. This flag is only allowed if the address is a post inc/decrement. (empty) Use the bus cycle for the current mode. <Src> is a register, (identifiers defined with 'rn'). <Address> The <Tflag> is allowed in 1 to 5 but not in the others. The <!flag> is allowed in 6 to 9 but not in the others. 10 is syntetic sugare for pc relative addressing. 1 [ <Addr> ] indirect register. 2 [ <Addr> ],#<Offset> indirect register with immediate post inc/decrement. 3 [ <Addr> ],<+/-> <RegOffset> 4 [ <Addr> ],<+/-> <RegOffset>, rrx 5 [ <Addr> ],<+/-> <RegOffset>,<ShiftOp> #<Expression> indirect register with register post inc/decrement. 6 [ <Addr>,#<Offset> ] indirect register with immediate pre inc/decrement. 7 [ <Addr>,<+/-> <RegOffset> ] 8 [ <Addr>,<+/-> <RegOffset>, rrx ] 9 [ <Addr>,<+/-> <regOffset>, <ShiftOp> #<Expression> ] indirect register with register pre inc/decrement. 10 <Expr> Translated into [pc,#<Offset>] where <Expr> = pc+<Offset> compensated for prefetching. <Addr> and <RegOffset> are a registers, (identifiers defined with 'rn'). <+/-> a plus or minus sign, or nothing which means plus. <Offset> is an expression which value fits in a 12-bit constant with a sign bit ,-4095 to +4095 inclusive. rrx see rrx. <ShiftOp> see ShiftOp. <!flag> ! <Addr> = <Addr> <+/-> Offset This flag is only allowed if the address is a pre inc/decrement. The <Addr> register is always updated if the <Address> is a post inc/decrement. (empty) Do not update the <Addr> register unless the <Address> is a post inc/decrement. %Float3Op Usage: Don't Summary: This is only a short description of some fpu instructions. Syntax: <Float3Op><Cond><Prec><Round> <Dst>,<Lhs>,<Rhs> where <Float3Op> is one of: adf <Dst> = <Lhs> + <Rhs> suf <Dst> = <Lhs> - <Rhs> rsf <Dst> = <Rhs> - <Lhs> muf <Dst> = <Lhs> * <Rhs> dvf <Dst> = <Lhs> / <Rhs> rdf <Dst> = <Rhs> / <Lhs> pow <Dst> = <Lhs> ** <Rhs> rpw <Dst> = <Rhs> ** <Lhs> rmf <Dst> = <Lhs> mod <Rhs> fml <Dst> = <Lhs> * <Rhs> fast multiplication fdv <Dst> = <Lhs> / <Rhs> fast division frd <Dst> = <Rhs> / <Lhs> fast reverse division pol <Dst> = arctan(<Lhs> / <Rhs>) <Cond> see Cond. <Prec> is one of: s Single precision (32-bit float). d Double precision (64-bit float). e Extended precision (96-bit float). <Round> is one of: p Round to plus infinity. m Round to minus infinity. z Round to zero. (empty) Round to nearest. <Dst> and <Lhs> are fpu registers, (identifiers defined with 'fn'). <Rhs> is one of: #<FloatExpression> Must evaluate to one of 0.0 1.0 2.0 3.0 4.0 5.0 10.0 or 0.5 <FpuRegister> Identifier defined with 'fn'. %Float2Op Usage: Don't Summary: This is only a short description of some fpu instructions. Syntax: <Float2Op><Cond><Prec><Round> <Dst>,<Rhs> where <Float2Op> is one of: mvf <Dst> = <Rhs> mnf <Dst> = - <Rhs> abs <Dst> = abs( <Rhs>) rnd <Dst> = rnd( <Rhs>) <Rhs> is rounded to an integer. sqt <Dst> = sqr( <Rhs>) Square root log <Dst> = log( <Rhs>) Log base 10. lgn <Dst> = lgn( <Rhs>) Log base e. exp <Dst> = e ** <Rhs> sin <Dst> = sin( <Rhs>) cos <Dst> = cos( <Rhs>) tan <Dst> = tan( <Rhs>) asn <Dst> = asn( <Rhs>) acs <Dst> = acs( <Rhs>) atn <Dst> = atn( <Rhs>) <Cond> see Cond. <Prec> is one of: s Single precision (32-bit float). d Double precision (64-bit float). e Extended precision (96-bit float). <Round> is one of: p Round to plus infinity. m Round to minus infinity. z Round to zero. (empty) Round to nearest. <Dst> is a fpu register, (identifiers defined with 'fn'). <Rhs> is one of: #<FloatExpression> Must evaluate to one of 0.0 1.0 2.0 3.0 4.0 5.0 10.0 or 0.5 <FpuRegister> Identifier defined with 'fn'. %adf E.g.: adfs f0,f1,f2 Summary: Floating point addition. See: Float3Op %suf E.g.: sufs f0,f1,f2 Summary: Floating point subtraction. See: Float3Op %rsf E.g.: rsfs f0,f1,#10.0 Summary: Reverse floating point subtraction. See: Float3Op %muf E.g.: mufs f0,f1,f2 Summary: Floating point multiplication. See: Float3Op %dvf E.g.: dvfs f0,f1,f2 Summary: Floating point division. See: Float3Op %rdf E.g.: rdfs f0,f1,#1.0 Summary: Reverse floating point division. See: Float3Op %pow E.g.: pows f0,f1,f2 Summary: Floating point power operation. See: Float3Op %rpw E.g.: rpws f0,f1,#10.0 Summary: Raise a float point constant to the power of a floating point register. See: Float3Op %rmf E.g.: rmfs f0,f1,f2 Summary: Floating point reminder. See: Float3Op %fml E.g.: fmls f0,f1,f2 Summary: Fast floating point multiplication. See: Float3Op %fdv E.g.: fdvs f0,f1,f2 Summary: Fast floating point division. See: Float3Op %frd E.g.: frds f0,f1,#1.0 Summary: Fast reverse floating point division. See: Float3Op %pol E.g.: pols f0,f1,f2 Summary: Float cartesian coordinate to angle. See: Float3Op %mvf E.g.: mvfs f0,#1.0 Summary: Floating point move. See: Float2Op %mnf E.g.: mnfs f0,#1.0 Summary: Floating point negated move, i.e., the second operand is negated. See: Float2Op %abs E.g.: abss f0,#1.0 Summary: Floating point absolute value. See: Float2Op %rnd E.g.: rnds f0,#1.0 Summary: Round floating value to integer, result in a floating point register. Use fix if the integer should be in a cpu register. See: Float2Op fix %sqt E.g.: sqts f0,#1.0 Summary: Floating point square root. See: Float2Op %log E.g.: logs f0,#1.0 Summary: Floating point log base 10. See: Float2Op %lgn E.g.: lgns f0,#1.0 Summary: Floating point log base e. See: Float2Op %exp E.g.: exps f0,#1.0 Summary: E raised to the power of a floating point register, or floating point constant. See: Float2Op %sin E.g.: sins f0,#1.0 Summary: Floating point sine. See: Float2Op %cos E.g.: coss f0,#1.0 Summary: Floating point cosine. See: Float2Op %tan E.g.: tans f0,#1.0 Summary: Floating point tangent. See: Float2Op %asn E.g.: asns f0,#1.0 Summary: Inverse floating point sine. See: Float2Op %acs E.g.: acss f0,#1.0 Summary: Inverse floating point cosine. See: Float2Op %atn E.g.: atns f0,#1.0 Summary: Inverse floating point tangent. See: Float2Op %FloatCmp Usage: Don't Summary: This is only a short description of some fpu instructions. Note: I'm not sure that this is correct! This is how the assembler treats the instructions, but it is possible that a precision is needed. Syntax: <FloatCmp><Cond><Prec><Round> <Lhs>,<Rhs> where <FloatCmp> is one of: cmf <Lhs> - <Rhs> cmfe <Lhs> - <Rhs> Generates an exception if unorded. cnf <Lhs> + <Rhs> cnfe <Lhs> + <Rhs> Generates an exception if unorded. <Cond> see Cond. <Lhs> is a fpu register, (identifiers defined with 'fn'). <Rhs> is one of: #<FloatExpression> Must evaluate to one of 0.0 1.0 2.0 3.0 4.0 5.0 10.0 or 0.5 <FpuRegister> Identifier defined with 'fn'. %cmf E.g.: cmf f0,#1.0 Summary: Floating point compare. See: FloatCmp cmfe %cmfe E.g.: cmfe f0,#1.0 Summary: Floating point compare. Cmfe raises an exception if the operands are unorded. See: FloatCmp cmf %cnf E.g.: cnf f0,#1.0 Summary: Floating point negated compare, i.e., the second operand is negated. See: FloatCmp cnfe %cnfe E.g.: cnfe f0,#1.0 Summary: Floating point negated compare, i.e., the second operand is negated. Cnfe raises an exception if the operands are unorded. See: FloatCmp cnf %fix E.g.: fixsz r0,f0 Summary: Fix rounds a floating points value to an integer and stores the result in a cpu register. Use rnd if the result should be stored in a floating point number. Syntax: fix<Cond><Prec><Round> <Dst>,<Rhs> <Cond> see Cond. <Prec> is one of: s Single precision (32-bit float). d Double precision (64-bit float). e Extended precision (96-bit float). <Round> is one of: p Round to plus infinity. m Round to minus infinity. z Round to zero. (empty) Round to nearest. <Dst> is a cpu register, (identifiers defined with 'rn'). <Rhs> is one of: #<FloatExpression> Must evaluate to one of 0.0 1.0 2.0 3.0 4.0 5.0 10.0 or 0.5 <FpuRegister> Identifier defined with 'fn'. %flt E.g.: fltsz f0,r0 Summary: Flt converts an integer in a cpu register to a float and stores the result in a fpu register. Syntax: flt<Cond><Prec><Round> <Dst>,<Rhs> <Cond> see Cond. <Prec> is one of: s Single precision (32-bit float). d Double precision (64-bit float). e Extended precision (96-bit float). <Round> is one of: p Round to plus infinity. m Round to minus infinity. z Round to zero. (empty) Round to nearest. <Dst> is a fpu register, (identifiers defined with 'fn'). <Rhs> is a cpu register, (identifiers defined with 'rn'). %rfs E.g.: rfs r0 Summary: Rfs copies the fpu's status register into a cpu register. The status register contains the following flags: bit 0: IVO invalid operation. bit 1: DVZ divide by zero. bit 2: OFL overflow. bit 3: UFL underflow. bit 4: INX inexact bit 5 to bit 15 Unused, read as zero. bit 16: IVO mask, set means interrupt enabled. bit 17: DVZ mask, set means interrupt enabled. bit 18: OFL mask, set means interrupt enabled. bit 19: UFL mask, set means interrupt enabled. bit 20 to bit 23 Unused, read as zero. bit 24 to bit 31 System id, where bit 31 set means floating point hardware, read only. Syntax: rfs<Cond> <Dst> <Cond> see Cond. <Dst> is a cpu register, (identifiers defined with 'rn'). %wfs E.g.: wfs r0 Summary: Wfs updates the fpu's status register with the value of a cpu register. The status register contains the following flags: bit 0: IVO invalid operation. bit 1: DVZ divide by zero. bit 2: OFL overflow. bit 3: UFL underflow. bit 4: INX inexact bit 5 to bit 15 Unused, read as zero. bit 16: IVO mask, set means interrupt enabled. bit 17: DVZ mask, set means interrupt enabled. bit 18: OFL mask, set means interrupt enabled. bit 19: UFL mask, set means interrupt enabled. bit 20 to bit 23 Unused, read as zero. bit 24 to bit 31 System id, where bit 31 set means floating point hardware, read only. Syntax: wfs<Cond> <Src> <Cond> see Cond. <Src> is a cpu register, (identifiers defined with 'rn'). %rfc E.g.: rfc r0 Summary: Rfc is a privileged instruction that reads the fpu's control register. An attempt to use it in user mode will cause a trap. I have no information about what the control register contains. Syntax: rfc<Cond> <Dst> <Cond> see Cond. <Dst> is a cpu register, (identifiers defined with 'rn'). %wfc E.g.: wfc r0 Summary: Wfc is a privileged instruction that updates the fpu's control register. An attempt to use it in user mode will cause a trap. I have no information about what the control register contains. Syntax: rfc<Cond> <Dst> <Cond> see Cond. <Dst> is a cpu register, (identifiers defined with 'rn'). %ldf E.g.: ldfs f0,[r0,#16] Summary: Ldf loads floating point values. Syntax: ldf<Cond><Prec> <Dst>,<Address><!flag> <Cond> see Cond. <Prec> is one of: s Single precision (32-bit float). d Double precision (64-bit float). e Extended precision (96-bit float). p Packed decimal (96-bit bcd-float). <Dst> is a fpu register, (identifiers defined with 'fn'). <Address> The <!flag> is allowed in the last last variants but not in the others. [ <Addr> ] indirect register. [ <Addr> ],#<Offset> indirect register with immediate post inc/decrement. [ <Addr>,#<Offset> ] indirect register with immediate pre inc/decrement. <Addr> is a registers, (identifiers defined with 'rn'). <Offset> is an expression which value fits 10-bit constant with a sign bit where the two lowes bits set to zero ,-1020 to +1020 inclusive but only multiples of four. <!flag> ! <Addr> = <Addr> + Offset, if increment, = <Addr> - Offset, if decrement. This flag is only allowed if the address is a pre inc/decrement. The <Addr> register is always updated if the <Address> is a post inc/decrement. (empty) Do not update the <Addr> register unless the <Address> is a post inc/decrement. %stf E.g.: stfs f0,[r0,#16] Summary: Stf stores floating point values. The rounding mode is always round to nearest, use a mvf before if another rounding mode is needed. Syntax: stf<Cond><Prec> <Src>,<Address><!flag> <Cond> see Cond. <Prec> is one of: s Single precision (32-bit float). d Double precision (64-bit float). e Extended precision (96-bit float). p Packed decimal (96-bit bcd-float). <Src> is a fpu register, (identifiers defined with 'fn'). <Address> The <!flag> is allowed in the last last variants but not in the others. [ <Addr> ] indirect register. [ <Addr> ],#<Offset> indirect register with immediate post inc/decrement. [ <Addr>,#<Offset> ] indirect register with immediate pre inc/decrement. <Addr> is a registers, (identifiers defined with 'rn'). <Offset> is an expression which value fits 10-bit constant with a sign bit where the two lowes bits set to zero ,-1020 to +1020 inclusive but only multiples of four. <!flag> ! <Addr> = <Addr> + Offset, if increment, = <Addr> - Offset, if decrement. This flag is only allowed if the address is a pre inc/decrement. The <Addr> register is always updated if the <Address> is a post inc/decrement. (empty) Do not update the <Addr> register unless the <Address> is a post inc/decrement. %ldc E.g.: ldc 10,c0,[r0,#16] Summary: Ldc loads a value to a coprocessor register. The fpu is coprocessor 1 so use ldf instead of ldc 1. Syntax: ldc<Cond><Lflag> <Cop><Dst>,<Address><!flag> <Cond> see Cond. <Cop> is the number of the coprocessor: 1 is the fpu. 2-14 don't know if they are assign to anything. 15 is cache control on an ARM3. <Lflag> is one of: (Note it is the coprocessor that decides what this flag means.) l This is a long transfer. (empty) This is a short transfer. <Dst> is a coprocessor register, (identifiers defined with 'cn'). <Address> The <!flag> is allowed in the last variant but not in the others. [ <Addr> ] indirect register. [ <Addr> ],#<Offset> indirect register with immediate post inc/decrement. [ <Addr>,#<Offset> ] indirect register with immediate pre inc/decrement. <Addr> is a register, (identifiers defined with 'rn'). <Offset> is an expression which value fits 10-bit constant with a sign bit where the two lowes bits set to zero ,-1020 to +1020 inclusive but only multiples of four. <!flag> ! <Addr> = <Addr> + Offset, if increment, = <Addr> - Offset, if decrement. This flag is only allowed if the address is a pre inc/decrement. The <Addr> register is always updated if the <Address> is a post inc/decrement. (empty) Do not update the <Addr> register unless the <Address> is a post inc/decrement. %stc E.g.: stc 10,c0,[r0,#16] Summary: Stc stores a value from a coprocessor register. The fpu is coprocessor 1 so use stf instead of stc 1. Syntax: stc<Cond><Lflag> <Cop><Src>,<Address><!flag> <Cond> see Cond. <Lflag> is one of: (Note it is the coprocessor that decides what this flag means.) l This is a long transfer. (empty) This is a short transfer. <Cop> is the number of the coprocessor: 1 is fpu. 2-14 don't know if they are assign to anything. 15 is cache control on an ARM3. <Src> is a coprocessor register, (identifiers defined with 'cn'). <Address> The <!flag> is allowed in the last variant but not in the others. [ <Addr> ] indirect register. [ <Addr> ],#<Offset> indirect register with immediate post inc/decrement. [ <Addr>,#<Offset> ] indirect register with immediate pre inc/decrement. <Addr> is a register, (identifiers defined with 'rn'). <Offset> is an expression which value fits 10-bit constant with a sign bit where the two lowes bits set to zero ,-1020 to +1020 inclusive but only multiples of four. <!flag> ! <Addr> = <Addr> + Offset This flag is only allowed if the address is a pre inc/decrement. The <Addr> register is always updated if the <Address> is a post inc/decrement. (empty) Do not update the <Addr> register unless the <Address> is a post inc/decrement. %cdp E.g.: cdp 2,3,c0,c1,c2 Summary Cdp is the coprocessor data instruction. Do not use it for coprocessor 1 as the fpu has its own mnemonics. Syntax: cdp<Cond> <Cop>,<Operator>,<Dst>,<Rhs>,<Lhs> or cdp<Cond> <Cop>,<Operator>,<Dst>,<Rhs>,<Lhs>,<Info> <Cond> see Cond. <Cop> is the number of the coprocessor: 1 is the fpu. 2-14 don't know if they are assign to anything. 15 is cache control on an ARM3. <Opcode> is the number of this opcode, 0 to 15 inclusive. <Dst>,<Rhs> and <Lhs> are coprocessor register, (identifiers defined with 'cn'). <Info> is the optional additional information field, 0 to 7 inclusive. It is set to zero if it is omitted. %mrc E.g.: mrc 2,3,r0,c1,c2 Summary Mrc moves a value from the cpu to the coprocessor. Do not use it for coprocessor 1 as the fpu has its own mnemonics. Syntax: mrc<Cond> <Cop>,<Operator>,<Dst>,<Rhs>,<Lhs> or mrc<Cond> <Cop>,<Operator>,<Dst>,<Rhs>,<Lhs>,<Info> <Cond> see Cond. <Cop> is the number of the coprocessor: 1 is the fpu. 2-14 don't know if they are assign to anything. 15 is cache control on an ARM3 see CachOp. <Opcode> is the number of this opcode, 0 to 7 inclusive. <Dst> is a cpu register, (identifiers defined with 'rn'). <Rhs> and <Lhs> are coprocessor register, (identifiers defined with 'cn'). <Info> is the optional additional information field, 0 to 7 inclusive. It is set to zero if it is omitted. %mcr E.g.: mcr 2,3,r0,c1,c2 Summary Mcr moves a value from the coprocessor to the cpu. Do not use it for coprocessor 1 as the fpu has its own mnemonics. Syntax: mrc<Cond> <Cop>,<Operator>,<Dst>,<Rhs>,<Lhs> or mrc<Cond> <Cop>,<Operator>,<Dst>,<Rhs>,<Lhs>,<Info> <Cond> see Cond. <Cop> is the number of the coprocessor: 1 is the fpu. 2-14 don't know if they are assign to anything. 15 is cache control on an ARM3 see CachOp. <Opcode> is the number of this opcode, 0 to 7 inclusive. <Dst> is a cpu register, (identifiers defined with 'rn'). <Rhs> and <Lhs> are coprocessor register, (identifiers defined with 'cn'). <Info> is the optional additional information field, 0 to 7 inclusive. It is set to zero if it is omitted. %CachOp Usage: Don't Summary: This is only a short description of how to control the cache on an ARM3. The information is taken from one article by Andrew Mell (Message-ID: <9108160241.AA17682@mole.gnu.ai.mit.edu>) and one by Michael Hardy (Message-ID: <9189@acorn.co.uk>). I have assumed that c0 and c1 are defined as coprocessor registers 0 and 1. Note: According to my knowledge the maximum coprocessor register is 15 not 31 as stated in Mell's article but I might be wrong. I also wonder if there are any mnemonic specified for this operations. mrc<Cond> 15,0,arm-register,control-register,c0 writes to the cache controller mcr<Cond> 15,0,arm-register,control-register,c0 reads from the cache controller The control registers are: register 0: 32 bit processor identity field bit 31-24 : Designer (41h = Acorn) bit 23-16 : Manufacturer (56h = vlsi) bit 15-8 : Part type (03h = arm3) bit 7-0 : Revision (0 = revision 0) register 1: cache flush writing any value to this register flushes the cache so an ultrafast cache flush is "mrc 15,0,r0,c1,c0". register 2: cache control (3 bit register) bit 0: high = cache on , low = cache off bit 1: high = shared supervisor/user address space low = separate supervisor/user address space bit 2: high = select monitor mode for program tracing with a logic analyser leave it low bit 3-31 : reserved register 3: cacheable areas register (32 bits) If bit n is set then the 2MBytes starting at n*2MBytes are cacheable. The default value stored is &FC007FFF, so ROM, the RAM disc and logical non-screen RAM are cacheable, but I/O space, physical memory and logical screen memory are not. register 4: updateable areas register (32 bits) If bit n is set then the 2MBytes starting at n*2MBytes are updateable. The default value stored is &00007FFF, so logical non-screen RAM is updateable, but ROM/CAM/DAG, I/O space, physical memory and logical screen memory are not. register 5: disruptive areas register (32 bits) If bit n is set then the 2MBytes starting at n*2MBytes are disruptive. The default value stored is &F0000000, so the CAM map is disruptive, but ROM/DAG, I/O space, physical memory and logical memory are not. This causes automatic flushing whenever MEMC's page mapping is altered, which allows programs written for the ARM2 (including RISC OS itself) to run unaltered, but at the expense of unnecessary flushing on page swaps. register 6-31: reserved