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Text File  |  1992-11-14  |  469 b   |  15 lines
  1. Newsgroups: sci.electronics
  2. Path: sparky!uunet!melpar!doherty
  3. From: doherty@melpar (Kevin Doherty)
  4. Subject: Re: Clock signal generator
  5. Organization: E-Systems, Melpar Division
  6. Date: Fri, 13 Nov 1992 14:43:01 GMT
  7. Message-ID: <Bxnsvq.FFo@melpar>
  8. References: <1992Nov12.203504.16474@ultb.isc.rit.edu>
  9. Lines: 4
  10.  
  11.  
  12.   I think you're looking for a phase locked loop circuit; that much I can
  13. figure out.  Unfortunately, I'm the wrong person to ask re: PLL specifics.
  14. Good luck.
  15.