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- Newsgroups: comp.unix.pc-clone.32bit
- Path: sparky!uunet!zaphod.mps.ohio-state.edu!swrinde!emory!gatech!nscf!wa4phy!sam
- From: sam@wa4phy.ampr.org (Sam Drinkard)
- Subject: Re: Cacheable address range on ISA 486's
- Message-ID: <1992Nov7.151306.326@wa4phy.ampr.org>
- Organization: Unix Business Solutions
- References: <1992Oct22.201908.5288@walter.bellcore.com> <1992Oct25.203602.2387@ksmith.uucp> <BwqMxn.26p@portal.hq.videocart.com> <913@felix.Sublink.Org> <1992Nov5.200108.6921@mdd.comm.mot.com> <92Nov5.164644est.42003@ois.db.toronto.edu> <1992Nov6.182902.18649@mdd.comm.mot.com>
- Distribution: na
- Date: Sat, 7 Nov 1992 15:13:06 GMT
- Lines: 31
-
- kelsey@mdd.comm.mot.com (Joe Kelsey) writes:
-
- [stuff deleted for brievity]
-
- >sockets plus two special 16M sockets (the so-called 32-bit sockets?)).
- >The cache configuration options allow you to install a 64K cache which
- >only covers 16M address space or a 256K cache which covers up to 64M
- >address space (it instructs you to put different chips in the TAG
- >sockets for each configuration.) The ADVANCED CHIPSET SETUP now
- >allows me to explicitly set any cacheable address range from 4M to 64M
- >in 4M increments.
-
- >Whew! Maybe an overly long-winded answer to a seemingly simple
- >question?
-
- >/Joe
- Joe, I have a "Magitronics" 486-33 isa bus board that does the same thing
- you describe, and has probably the same simm configuration. I've been
- rather loosely following this thread, and have gotten curious if in fact,
- the tag ram on this board will support the 64 meg like it allows you to
- select in the setup. Currently only have 8 megs on board, but planning
- on increasing to at least 32 megs one of these days soon.. kinda waiting
- to see if someone else has success before ploping down the $ for the
- simm's tho..
-
- sam
-
- --
- Sam Drinkard | internet: wa4phy!sam@galois.nscf.org
- WA4PHY | internet: sam@wa4phy.nscf.nscf.org
-
-