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- Newsgroups: comp.unix.pc-clone.32bit
- Path: sparky!uunet!mdisea!kelsey
- From: kelsey@mdd.comm.mot.com (Joe Kelsey)
- Subject: Re: Cacheable address range on ISA 486's
- Message-ID: <1992Nov6.182902.18649@mdd.comm.mot.com>
- Sender: news@mdd.comm.mot.com
- Organization: Motorola, Mobile Data Division - Seattle, WA
- References: <1992Oct22.201908.5288@walter.bellcore.com> <1992Oct25.203602.2387@ksmith.uucp> <BwqMxn.26p@portal.hq.videocart.com> <913@felix.Sublink.Org> <1992Nov5.200108.6921@mdd.comm.mot.com> <92Nov5.164644est.42003@ois.db.toronto.edu>
- Distribution: na
- Date: Fri, 6 Nov 1992 18:29:02 GMT
- Lines: 52
-
- In <92Nov5.164644est.42003@ois.db.toronto.edu> fche@db.toronto.edu ("Frank Ch. Eigler") writes:
- >What happens if the cache indeed has only a few address bits in its tag
- >RAM, say 22 bits, but physical memory may extend above 2^22 bytes? Are
- >there boards that *don't* at least *check* the rest of the bits of CPU
- >address lines, thus whose cache tag may falsely match an address above
- >2^22 with one below and return the wrong data?
-
- I don't know if I completely understand your question, but I think I
- can respond by describing my situation in more detail.
-
- Most BIOS setup programs for boards with EXTERNAL caches have some
- sort of option under the ADVANCED CHIPSET SETUP menu that has
- something vaguely to do with how much of the physical board address
- space the EXTERNAL cache can map. Remember, with all 486 machines,
- the chip has an internal cache, so the external cache supplements
- this, allowing you to buy, say, 70ns SIMM's instead of 40ns or 50ns.
- The board designers have to decide how much physical memory they plan
- to allow someone to use. Early designers seem to have believed that
- no one in their right mind can ever effectively use more than 16M of
- physical memory. (I encounter this attitude every time I talk to the
- DOS-centric people who sell PC's.)
-
- Thus, the first motherboard I had had 8 SIMM sockets. I populated
- bank 0 with 4M SIMM's initially. Then, a friend offered me another
- set of SIMM's at a great price, so I figured, what the heck, now I can
- set up for fast page mode and run some really big X Window programs.
- Unfortunately, the motherboard designers didn't fully implement the
- external cache. However, they left tantalizing traces, including an
- ADVANCED CHIPSET SETUP menu option labelled MEMORY ABOVE 16M
- CACHEABLE. If you turn this option on *without* installing the extra
- TAG RAM chip mentioned in the manual, when UNIX boots, it hangs almost
- immediately due to getting bad data returned from incorrect cache
- hits. So a naive answer to your question: Yes, if you go to the
- trouble of setting the incorrect BIOS options, then, indeed, the cache
- returns the incorrect data.
-
- However, even with an extra TAG RAM chip installed, the system did not
- work. It turned out that I got one of the last borads in that
- production run. The new boards have a completely new layout,
- including the ability to put 64M of physical memory on board (8 SIMM
- sockets plus two special 16M sockets (the so-called 32-bit sockets?)).
- The cache configuration options allow you to install a 64K cache which
- only covers 16M address space or a 256K cache which covers up to 64M
- address space (it instructs you to put different chips in the TAG
- sockets for each configuration.) The ADVANCED CHIPSET SETUP now
- allows me to explicitly set any cacheable address range from 4M to 64M
- in 4M increments.
-
- Whew! Maybe an overly long-winded answer to a seemingly simple
- question?
-
- /Joe
-