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- Path: sparky!uunet!auspex-gw!guy
- From: guy@Auspex.COM (Guy Harris)
- Newsgroups: comp.sys.sun.hardware
- Subject: Re: SPARCClassic
- Message-ID: <15475@auspex-gw.auspex.com>
- Date: 13 Nov 92 01:44:00 GMT
- References: <1dpbvnINN1j5@almaak.usc.edu> <1992Nov11.075828.6425@proponent.com> <1992Nov12.213143.1454@boole.uucp>
- Sender: news@auspex-gw.auspex.com
- Organization: Auspex Systems, Santa Clara
- Lines: 21
- Nntp-Posting-Host: auspex.auspex.com
-
- >How does a 50MHz chip achieve 59.1 MIPS?
-
- By defining MIPS as...
-
- >I know that MIPS is about the sloppiest term around, but what
- >can they possible mean when they use it here?
-
- ... "the number of times faster than a VAX-11/780 that the SPARCclassic
- runs benchmark XXX, when that benchmark is compiled with compiler
- version YYY and run under version ZZZ of operating system WWW on the VAX
- and compiled with compiler AAA and run under version BBB of operating
- system CCC on the SPARCclassic".
-
- Remember, in the phrase "this machine has N MIPS", "MIPS" stands for
- "Meaningless Indicator of Processor Speed"; the fact that it also
- happens to be the acronym for "Millions of Instructions Per Second" is
- best thought of as being purely coincidence, these days, as it has
- nothing to do with the number of millions of instructions some processor
- can run per second.
-
- (I.e., it appears to be even sloppier than you thought....)
-