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- Newsgroups: comp.sys.sgi
- Path: sparky!uunet!haven.umd.edu!darwin.sura.net!spool.mu.edu!snorkelwacker.mit.edu!bloom-picayune.mit.edu!athena.mit.edu!ertas
- From: ertas@athena.mit.edu (Mehmet D Ertas)
- Subject: Re: Increased Prices for Memory
- Message-ID: <1992Nov8.184148.14312@athena.mit.edu>
- Sender: news@athena.mit.edu (News system)
- Nntp-Posting-Host: e40-008-9.mit.edu
- Organization: Massachusetts Institute of Technology
- References: <1992Nov5.195012.5289@ringer.cs.utsa.edu> <1992Nov6.140610.26884@athena.mit.edu> <1992Nov7.051153.26035@ringer.cs.utsa.edu>
- Date: Sun, 8 Nov 1992 18:41:48 GMT
- Lines: 46
-
- In article <1992Nov7.051153.26035@ringer.cs.utsa.edu>, senseman@ricky.brainlab.utsa.edu (David M. Senseman) writes:
- |> In article <1992Nov6.140610.26884@athena.mit.edu> ertas@athena.mit.edu (Mehmet D Ertas) writes:
- |> >Yes, for the same reason, Kingston 3rd
- |> >party memory expansion kits for R4k (64 MB)
- ^^^^^^^^^^^^^^^^^
- |> >have also increased by $350. By the way,
- |> >I was also told that the design of
- |> >these have changed to include drivers in
- |> >order to eliminate any possible bus loading
- |> >problems, due to their unconventional(!) design.
- |> >The new design is available now.
- |> >
- |>
- |> Yikes! I just placed an order with Impediment on Thursday and we are suppose
- |> to receive the 32 MB upgrade package (for the R4K Indigo) on Monday. This is
- |> the first I have heard of including "drivers" with the RAM so as not to load
- |> the bus. I have no idea which type of memory Impediment is sending (all I
- |> know is that it's going to cost me more that it would have last week :(
- |>
- |> Am I correct in assuming that I should be able to easily tell whether these
- |> chips are the old or new design? (i.e. are the drivers are easy to spot?).
- |> Should I refuse delivery if there are the "old" design?
-
- As far as I know, this is not a potential problem for the 32MB kits, since
- they occupy 8MB/slot on the board. However, 64MB kits occupy 16MB/slot,
- using THE SAME CHIPS AS BUILDING BLOCKS (i.e. 4Mbit ones, instead of 16Mbit, I suppose),
- this means that the bus load will be twice as much on these slots.
- (Especially on the lower bits of the address bus, they will have to drive 4 chips
- instead of 1)
- I'm pretty sure that there's nothing you have to worry about for the
- 32MB memory. Even the "older" 64MB design, as far as Impediment has told me,
- worked just fine, but they've changed the design to make sure that there's
- not even a little doubt on SGI's and the customer's side that they didn't
- perform properly.
-
-
- Deniz Ertas
-
-
- |>
- |> Can anyone (Dave?) elaborate on what's going on? Thanks.
- |> --
- |> David M. Senseman, Ph.D. | A man who has never gone to school may steal
- |> (senseman@lonestar.utsa.edu) | from a freight car; but if he has a university
- |> Division of Life Sciences | education, he may steal the whole railroad.
- |> UT San Antonio | Theodore Roosevelt (1858-1919)
-