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- Newsgroups: comp.sys.ibm.pc.hardware
- Path: sparky!uunet!utcsri!newsflash.concordia.ca!sifon!thunder.mcrcim.mcgill.edu!homer.cs.mcgill.ca!storm
- From: storm@cs.mcgill.ca (Marc WANDSCHNEIDER)
- Subject: Re: Cache speed for 50 MHz 486DX?
- Message-ID: <1992Nov11.042817.9464@cs.mcgill.ca>
- Sender: news@cs.mcgill.ca (Netnews Administrator)
- Organization: SOCS - McGill University, Montreal, Canada
- References: <1992Nov4.162247.10869@lth.se> <92312.160559REE700A@MAINE.MAINE.EDU>
- Date: Wed, 11 Nov 1992 04:28:17 GMT
- Lines: 19
-
- In article <92312.160559REE700A@MAINE.MAINE.EDU> REE700A@MAINE.MAINE.EDU writes:
- >
- >I am told 5 nS tags (commonly built into controllers for direct mapped) and 10-
- >12 nS cache SRAMS. You just bought a DX50 that will be outperformed by (or at
- >least matched by) DX33's, as well as DX2/50's! Thank god (or whatever) that
- >the internal 8K cache is fairly effective!
-
- Except that Intel refuses to embrace Copy-back caching, which means
- that, unless your secondary cache is a good one with copy back caching,
- performance will suffer big time.
-
- ToodlepIP!
- Marc 'em.
-
- --
- storm@cs.mcgill.ca McGill University "-- Attack ships on
- Marc Wandschneider Montreal, CANADA fire "
- Any opinions expressed are not mine, but those of the Demon Lord
- Yeegeheeegenogohugu who possessed me whilst I munched on Raisin Bran.
-