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- Path: sparky!uunet!mcsun!news.funet.fi!hydra!karell
- From: karell@cs.Helsinki.FI (Esa Karell)
- Newsgroups: comp.sys.dec
- Subject: Alpha questions
- Message-ID: <31486@hydra.Helsinki.FI>
- Date: 12 Nov 92 20:15:12 GMT
- Organization: University of Helsinki, Finland
- Lines: 33
-
- I've only seen the ads on trade rags so I'd like
- to ask a few questions.
-
- 1) How parallel is Alpha? Can it execute more than
- 1 instruction/cycle (say, yes )? If yes, how many
- optimal/average?
-
- 2) How many instructions are there?
-
- 3) How scalable it is with clock rate? 200 sounds
- quite steep. Can you *easily* (means, still use
- the same technology) jack it up to say 400?
- Is it CMOS?
-
- 4) How big are icache and dcache?
- Does it vary on any of the currently introduced boxes?
-
- 5) The ad said that also SV(R4?) *IX is (yeah, it really did
- say *is* not will :-) available besides OSF/1.
- Who did this for Alpha and any details on it?
-
- 6) Greetings to dec mktg. Couldn't you possibly come up
- with a more pathetic way to push this chip than
- by tooting this 4 ??? ??? ??? whatever number.
- And think that some poor sobs may actually buy the
- propaganda that this box is 4 <whatever> times
- better than what they have now....
-
-
- --
-
- Esa Karell karell@cs.Helsinki.FI
- Tel. +358-0 513 081 /home
-