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- From: mascot@bnr.ca (Scott Mason)
- Newsgroups: comp.sys.amiga.hardware
- Subject: Re: 50MHz 68040 BSC Accelerator system
- Message-ID: <1992Nov5.194720.5287@bnr.ca>
- Date: 5 Nov 92 19:47:20 GMT
- References: <reaper.720898133@garfield.catt.ncsu.edu> <1992Nov4.204327.14987@mnemosyne.cs.du.edu> <reaper.720920082@garfield.catt.ncsu.edu>
- Sender: news@bnr.ca (usenet)
- Organization: Bell-Northern Research, Ottawa, Ontario, Canada
- Lines: 22
- Nntp-Posting-Host: bcara204
-
- In article <reaper.720920082@garfield.catt.ncsu.edu> reaper@garfield.catt.ncsu.edu (Jason Butler) writes:
- >jjsmith@nyx.cs.du.edu (Jonathan J. Smith) writes:
- >
- >>In article <reaper.720898133@garfield.catt.ncsu.edu> reaper@garfield.catt.ncsu.edu (Jason Butler) writes:
- >>>The 25 MHz '040 _is_ 50 MHz(50 internal, 25 external). All internal '040
- >>>operations run at 50 MHz. Maybe this is the reason, don't know.
-
- >>Are you Absolutly sure about that? TO my knowledge the 68040 HAS never been double clocked.
- >>and runs at a 25Mhz or 33Mhz internally the same as the external clock..
-
- >I think I'm sure. One of the Commodore guys posted about it just a few days
- >ago. Someone from C=!! Set us straight.
-
- I'm not from C=. Nevertheless, I have designed w/ the 68040. It uses
- two clocks, a Bus Clock (25 | 33 MHz) and a Processor Clock (2X BCLK).
- Motorola describes the 68040 by the BCLK frequency. The PCLK is
- generated externally, unlike the 486DX2.
-
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