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- Newsgroups: comp.parallel
- Path: sparky!uunet!cs.utexas.edu!swrinde!gatech!hubcap!fpst
- From: karhinen@cc.helsinki.fi (Anssi Karhinen)
- Subject: KSR coherency
- Message-ID: <1992Nov5.131353.20342@hubcap.clemson.edu>
- Apparently-To: comp-parallel@mcsun.EU.net
- Sender: fpst@hubcap.clemson.edu (Steve Stevenson)
- Organization: University of Helsinki
- X-Newsreader: TIN [version 1.1 PL6]
- Date: Thu, 5 Nov 1992 07:13:17 GMT
- Approved: parallel@hubcap.clemson.edu
- Lines: 11
-
-
- There have been some postings in this group that describe
- the function of the ALLCACHE-memory on the KSR 1 in detail.
- I have missed one detail or it hasn't been mentioned.
-
- The machine has 256 KB first level I- and D-caches. How are these
- caches kept coherent with the 32 MB ALLCACHE memory in each PE?
-
- Many thanks, Anssi
-
-
-