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- Newsgroups: comp.os.misc
- Path: sparky!uunet!ukma!wupost!uwm.edu!ux1.cso.uiuc.edu!csrd.uiuc.edu!sp90.csrd.uiuc.edu!grout
- From: grout@sp90.csrd.uiuc.edu (John R. Grout)
- Subject: Re: Processes and Translation Look-Aside Buffers
- Message-ID: <1992Nov6.170831.28384@csrd.uiuc.edu>
- Sender: news@csrd.uiuc.edu
- Reply-To: j-grout@uiuc.edu
- Organization: UIUC Center for Supercomputing Research and Development
- References: <Bx7oDL.507@beach.csulb.edu> <Bx99Eq.Cpp@pix.com>
- Date: Fri, 6 Nov 92 17:08:31 GMT
- Lines: 28
-
- stripes@pix.com (Josh Osborne) writes:
-
- >For cache there is a 3rd choice, you can use phyical addresses rather then
- >vert. ones (at the cost of not being able to overlap cache look-up and
- >VM maping)
-
- I have seen general statements to this effect in _many_ different
- places (even a few textbooks)... it is _not_ true in all cases!
-
- If you have a first-level, physically-addressed direct-mapped cache of
- the machine's page size (e.g., an on-chip cache), you _can_ overlap
- the cache and TLB look-ups... split the virtual address by feeding the
- virtual page offset (the _same_ as the physical page offset) to the
- cache and the virtual page number to the TLB... if the TLB hits and
- the cache hits (tentatively), compare the physical page number
- returned from the TLB hit with the physical page number from the cache
- line (_after_ the time-consuming parts of both operations are done).
- If the physical page numbers match (the common case), you have a valid
- cache hit and can go ahead with your operation.
-
- Hennessy and Patterson talk about this in their "Computer
- Architecture: A Quantitative Approach". Many RISC chips (including
- the new DEC 21064 Alpha chip) use this technique.
-
- --
- John R. Grout j-grout@uiuc.edu
- University of Illinois, Urbana-Champaign
- Center for Supercomputing Research and Development
-