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- Newsgroups: comp.lang.vhdl
- Path: sparky!uunet!destroyer!gatech!hubcap!ncrcae!bygate
- From: bygate@ncrcol.ColumbiaSC.NCR.COM (Terrence A. Bygate)
- Subject: Re: Subset of VHDL for synthesis.
- Message-ID: <1992Nov10.153804.7691@ncrcae.ColumbiaSC.NCR.COM>
- Nntp-Posting-Host: whistler.columbiasc.ncr.com
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- References: <3200@ucl-cs.uucp>
- Date: Tue, 10 Nov 92 20:38:04 GMT
- Lines: 32
-
- Meyer E. Nigri (M.Nigri@cs.ucl.ac.uk) wrote:
- :
- : I would like to know the present state regarding a formal definition
- : for a subset of VHDL aiming at synthesis.
- :
- : Meyer.
- :
- : |University College London |Internet:mnigri%cs.ucl.ac.uk@nsfnet-relay.ac.uk|
-
- The primary problem with defining a subset is that the target is
- always moving. At best, the subset would be valid six months, depending
- on which synthesis tool you were using. I have been using Synopsys for
- about 1.5 years, and with each release (and I have been through 3-4
- releases), the synthesis tool is able to read in more and more VHDL
- constructs.
-
- Also, some synthesis tools are starting to be able to do true high level
- synthesis. Albeit very expensive, Silcon1076 from LSI (~ US$256 K per seat),
- will read a high level description (ie, a behavioral description without
- any implied clocks) and then generate RTL VHDL, which is then fed into
- Synopsys.
-
- I am sure it is only a matter of time before other tool vendors will
- offer the same functionality.
-
- Terry.
- --
- Terrence A. Bygate 803-791-6492 | "A problem is nothing but an
- Multiprocessor Systems Business Unit | opportunity dressed in work
- NCR Corporation - 3500 Module Development | clothes" -borrowed
- ---------------------------------------------+----------------------------------
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