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- Newsgroups: comp.lang.vhdl,comp.lang.verilog,comp.sys.super
- Path: sparky!uunet!hela.iti.org!usc!elroy.jpl.nasa.gov!dank
- From: dank@blacks.jpl.nasa.gov (Daniel R. Kegel)
- Subject: HDL models or driver chips for HIPPI, anyone?
- Message-ID: <dank.720994184@blacks>
- Sender: news@elroy.jpl.nasa.gov (Usenet)
- Nntp-Posting-Host: blacks.jpl.nasa.gov
- Organization: Image Analysis Systems Group, JPL
- Date: Thu, 5 Nov 1992 20:09:44 GMT
- Lines: 16
-
- Hi,
- we're considering using HIPPI to connect several custom-built
- signal processing boards together. Has anyone out there written
- functional models in Verilog or VHDL for the HIPPI physical layer?
-
- Also, does anyone know of good line driver/receiver chips for HIPPI?
- I'd be interested in hex or octal chips; the only chips I remember offhand
- are the 10116 triple line receivers etc., which aren't very dense.
- It would be especially nice if the drivers/receivers also included
- level shifters to translate from HIPPI's ECL levels to CMOS levels that
- can be used with FPGA's.
-
- Please respond to dank@blacks.jpl.nasa.gov.
- I will summarize any replies.
- Thanks!
- Dan Kegel
-