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- Newsgroups: comp.lang.verilog
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- From: leung@DSG.Tandem.COM (Steven Leung)
- Subject: Re: Avoiding inertial delay in delay lines
- Message-ID: <1992Nov12.163116.17205@dsg.tandem.com>
- Originator: leung@bittemple
- Sender: news@dsg.tandem.com
- Nntp-Posting-Host: bittemple
- Organization: Tandem Computers
- References: <1992Nov12.053306.12799@afterlife.ncsc.mil> <1992Nov12.142615.10697@m.cs.uiuc.edu>
- Date: Thu, 12 Nov 1992 16:31:16 GMT
- Lines: 25
-
-
- smb@afterlife.ncsc.mil (Steve M. Burinsky) writes:
-
- >I need to simulate delay lines in order to model a bus interface. The
- >solution seems obvious -- use a net delay. However, the signal I need
- >to delay has pulse widths (w) which are shorter than the delay time (d);
- >that is w < d. The problem is that inertial delay causes the short pulse
- >to disappear within the delay. ...
-
- I think Verilog's stated delay model is inertia, but I found out from my
- experiments (with 1.6a) that the non_blocking assignment _plus_ delay
- control after the assignment operator has the same effect of transport delay.
- Since I don't know whether either Cadence or OVI has formally stated support
- for transport delay model, so I don't know whether this is a (happy) coincident
- or there may be some limitations I didn't know or they may change in the
- future version or it may not work with another Verilog simulator or ... But
- you can try this:
-
- a <= #10 b; /* transport delay */
-
- Steven
- --
- 328. Seek opportunity, not security. ...
- - Life's Little Instruction Book by H. J. Brown, Jr.
-
-