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- From: yegna@cat.syr.edu (Yegnashankar Parasuram)
- Subject: MOS threshold voltage ...
- Message-ID: <1992Nov11.211230.4289@newstand.syr.edu>
- Organization: CASE Center, Syracuse University
- Date: Wed, 11 Nov 92 21:12:29 EST
- Lines: 30
-
- Hi,
-
- I understand the threshold voltage of the P and N MOSFETs can be varied
- during the fabrication process.
-
- For an NMOS FET Vt = 0.809 volts (SPICE model)
-
- What is the lowest threshold voltage that most fabrication processes
- can achieve ? Can it be reduced to say 0.3 volts ...
- Are there any disadvantages in reducing it ???
-
- Thanks,
-
- -Yegna
-
- #########################################################################
-
- The contents of this article are the author's own views - they do not
- represent the view of any organisation such as the CASE centre or
- Syracuse University.
-
- #########################################################################
- # Yegnashankar Parasuram. #
- # Graduate Student at CE Department of Syracuse University. #
- # Office : 2-128, Centre for Science & Technology. #
- # email : yegna@cat.syr.edu. #
- #########################################################################
-
- "THERE IS NOTHING THAT CANNOT BE DONE, UNLESS YOU THINK IT CAN'T BE DONE"
-
-