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- From: bayko@mercury.cs.uregina.ca (John Bayko)
- Subject: Re: What's RIGHT with stack machines (Was Re: What's wrong...)
- Sender: news@sue.cc.uregina.ca
- Message-ID: <1992Nov14.003355.704321@sue.cc.uregina.ca>
- Date: Sat, 14 Nov 1992 00:33:55 GMT
- References: <Bx5AIr.EAy.2@cs.cmu.edu> <1992Nov11.134556.20150@super.org> <1992Nov12.204852.807@boole.uucp>
- Organization: University of Regina, SK, Canada
- Keywords: stack computers, embedded control, AT&T, Crisp, Hobbit
- Lines: 44
-
- In article
- <1992Nov12.204852.807@boole.uucp>
- NetCmmnd@boole.uucp (System Administrator)
- writes:
- >Where are the Hobbit people in this thread?
-
- I don't have anything on the Hobbit, but here's a (really very)
- brief description of its predecessor from the Great Microprocessor list...
- I doubt it's really useful, and probably not error free, but hopefully
- interesting...
-
-
- Great Microprocessors of the Past and Present (V 4.0.0)
-
- [...]
-
- Part III: AT&T CRISP, CISC amongst the RISC (1987)
-
- The AT&T CRISP was inspired by the Bell Labs C Machine project,
- aimed at a design optimised for the C language. Since C is a stack
- based language, the processor is optimised for memory to memory stack
- based execution, and has no user visible registers (stack pointer is
- modified by special instructions, an accumulator is in the stack), with
- the goal of simplifying the compiler as much as possible.
- Instead of registers, a thirty-two entry 32 bit two ported stack
- cache is provided. This is similar to the stack cache of the AMD 29000
- (in CRISP it's much smaller but is easily expandable), but CRISP has no
- global registers. Addresses can be memory direct or indirect (for
- pointers) relative to the stack pointer without extra instructions or
- operand bits. The cache is not optimised for multiprocessors.
- CRISP has a 512 byte instruction prefetch buffer,
- but decodes the variable length (2, 6 or 10 byte) instructions into a
- thirty-two entry decoded instruction cache. Branches are not delayed,
- and a prediction bit directs speculative branch execution. The decode
- unit folds branches into the decoded instructions, so a predicted
- branch does not take any extra clock cycles, saving execution time. The three
- stage execution unit takes instructions from the decode cache. Results
- can be forwarded when available to any prior stage as needed.
- Though CISC in philosophy, the CRISP is greatly simplified compared
- to traditional CISC designs, and features some very elegant design
- features. AT&T prefers to call it a RISC processor, and performance is
- comparable to RISC designs.
-
- John Bayko.
-