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- From: drdavis@u.cc.utah.edu (Darren R. Davis)
- Subject: Registerless processor
- Message-ID: <1992Nov13.181654.11692@fcom.cc.utah.edu>
- Sender: news@fcom.cc.utah.edu
- Organization: University of Utah Computer Center Student Mail Machine
- Date: Fri, 13 Nov 92 18:16:54 GMT
- Lines: 19
-
- I have been pondering an idea for a machine architecture. A processor
- that has no registers. I am familiar with some architectures that have
- done this. My twist on this theme is to have a very large cache on chip
- for memory locations (effectivelly becoming registers). This goes
- against the RISC idea of having very large register sets with load store
- instructions. This machine would just reference memory, and the most
- common addresses becoming cached internally to the processor giving very
- fast access. Does anyone know of such a machine, and what are your
- thoughts on this kind of architecture. I envision the cache being
- something like 8K or greater giving a large effective register set.
-
- This machine idea seems very Turing like in that it has a large memory
- space and small control structure. If machine instructions as well as
- memory values remain on chip operations should be very quick.
-
-
-
- The one processor I know of is the TI9900 I believe, but it does not
- have all the cache stuff.
-