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- Newsgroups: comp.arch
- Path: sparky!uunet!ukma!darwin.sura.net!zaphod.mps.ohio-state.edu!menudo.uh.edu!sugar!ficc!peter
- From: peter@ferranti.com (peter da silva)
- Subject: Re: why no register + register addressing mode in R3000
- Message-ID: <id.V9VU.1AE@ferranti.com>
- Organization: Xenix Support, FICC
- References: <18938@ucdavis.ucdavis.edu> <endecotp.721329802@cs.man.ac.uk>
- Date: Tue, 10 Nov 1992 17:26:36 GMT
- Lines: 32
-
- In article <endecotp.721329802@cs.man.ac.uk> endecotp@cs.man.ac.uk (PB Endecott (PhD SFurber)) writes:
- > Of course for a load, you do have two read ports available. Would anyone
- > consider an architecture with non-symetrical addressing modes, where loads
- > can do register+constant or register+register, but stores can do
- > register+constant only?
-
- Why not, if it gives you more performance? It's simple enough to get the
- compiler to deal with it, so most programmers would never see it.
-
- > Another feature that some processors have and others don't is
- > auto-indexing.
-
- I take it this is another name for autoincrement/autodecrement, or is
- it something I don't know about?
-
- > During loads, this requires an extra write port (or an
- > extra cycle) to put the modified value back in the register; but during
- > stores the write port is not used for data. So how about an architecture
- > with autoindexing for stores but not for loads ?
-
- This would be less useful, since most of the time autoin*ing is used for
- reading a data stream, but sure... why not? It'd make memory-memory block
- moves faster, and they'e very common. Probably improve your dhrystone
- rating, too. :->
-
- Another question is, is there any *other* use for the extra read/write
- ports? Could they be used elsewhere?
- --
- Peter da Silva / 77487-5012 USA / +1 713 274 5180
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