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- Xref: sparky comp.arch:10574 comp.lang.forth:3469
- Newsgroups: comp.arch,comp.lang.forth
- Path: sparky!uunet!sun-barr!cs.utexas.edu!uwm.edu!rpi!psinntp!psinntp!ficc!peter
- From: peter@ferranti.com (peter da silva)
- Subject: Re: What's RIGHT with stack machines
- Message-ID: <id.D6UU.5Z@ferranti.com>
- Organization: Xenix Support, FICC
- References: <Bx5AIr.EAy.2@cs.cmu.edu> <1992Nov4.103008.2641@Informatik.TU-Muenchen.DE> <MIKE.92Nov9004026@guam.vlsivie.tuwien.ac.at>
- Date: Mon, 9 Nov 1992 16:28:34 GMT
- Lines: 27
-
- In article <MIKE.92Nov9004026@guam.vlsivie.tuwien.ac.at> mike@vlsivie.tuwien.ac.at (Michael Gschwind) writes:
- > But what do you do when you get to things like CSE? DUP
- > DUP SWAP SWAP ROT? Hardly efficient! 2 memory accesses for DUP, 4 for
- > swap, 6 for ROT.
-
- Let's see, with a 16 element stack buffer, 0 or 1 memory access for dup
- (mostly 0), and 0 for swap or rot.
-
- > Once again, with technology of 10 years ago, they were nice,
- > but it does pay to allocate registers and do scheduling, AND WE HAVE
- > THE TECHNOLOGY NOW to do it.
-
- If you can afford to compile your code for each new processor, yes. Otherwise
- you have to assume that most code will use the scheduling that was best for
- the first generation of the chip. Outside of engineering-class workstations
- (a vanishingly small proportion of the total end-user micro market: PCs and
- game machines clobber it by orders of magnitude) this is the normal case,
- and in embedded systems (almost all the rest of the market) it's highly cost-
- effective to minimize code size: ROMS are slow and expensive.
-
- I predict that before too long all high performance commodity micros will do
- scheduling at runtime.
- --
- % Peter da Silva % 77487-5012 % +1 713 274 5180 %
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