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- From: endecotp@cs.man.ac.uk (PB Endecott (PhD SFurber))
- Newsgroups: comp.arch
- Subject: Re: why no register + register addressing mode in R3000
- Message-ID: <endecotp.721329802@cs.man.ac.uk>
- Date: 9 Nov 92 17:23:22 GMT
- References: <18938@ucdavis.ucdavis.edu>
- Sender: news@cs.man.ac.uk
- Lines: 50
-
- kong@ece.ucdavis.edu (Timothy Kong) writes:
-
- >The Mips R2/3/4000 has the register + offset addressing mode, i.e.
- >"load Rx,offset(Ra)," where offset is a 16-bit constant. Why doesn't it
- >have the more flexible "load Rx,Ra,Rb," where effective address = Ra + Rb?
- >Since either way effective address calculation needs an addition, the
- >reg.+reg. mode shouldn't require any more hardware. Am I missing something?
- >The Sparc has the reg.+reg. mode.
-
- >I have seen code where a "load Rx,Ra,Rb" would reduce instruction
- >count, and so the argument that such an instruction is rarely used
- >wouldn't make sense.
-
- >Timothy Kong
- >kong@eecs.ucdavis.edu
-
-
- Although it's true that both register+offset and register+register modes
- require an addition, you haven't allowed for the fact that an extra
- register read has to take place. Normally most microprocessors have two
- read ports and one write port on the register file, which is exactly what
- is required for three address arithmetic/logical operations. When you
- execute a store instruction, one read port is used for the data value, and
- the other for the address register.
-
- If you want to implement register+register addressing, you have two main
- choices :
-
- - Add a third read port. This increases the size of your register file by
- about 25%-ish, plus another set of decoders. The question you must ask is,
- would that extra silicon be better used for increasing the cache size, or
- just keeping the die cost down ?
-
- - Insert an extra cycle and read the registers in two goes. Ignoring the
- effect of cache misses etc. this takes the same number of cycles as doing
- an explicit add in a separate instruction - provided you have enough
- registers.
-
- Of course for a load, you do have two read ports available. Would anyone
- consider an architecture with non-symetrical addressing modes, where loads
- can do register+constant or register+register, but stores can do
- register+constant only?
-
- Another feature that some processors have and others don't is
- auto-indexing. During loads, this requires an extra write port (or an
- extra cycle) to put the modified value back in the register; but during
- stores the write port is not used for data. So how about an architecture
- with autoindexing for stores but not for loads ?
-
- -- Phil.
-