home *** CD-ROM | disk | FTP | other *** search
/ NetNews Usenet Archive 1992 #26 / NN_1992_26.iso / spool / comp / arch / 10557 < prev    next >
Encoding:
Text File  |  1992-11-09  |  1.4 KB  |  30 lines
  1. Newsgroups: comp.arch
  2. Path: sparky!uunet!ferkel.ucsb.edu!taco!gatech!darwin.sura.net!zaphod.mps.ohio-state.edu!sdd.hp.com!ux1.cso.uiuc.edu!csrd.uiuc.edu!sp90.csrd.uiuc.edu!grout
  3. From: grout@sp90.csrd.uiuc.edu (John R. Grout)
  4. Subject: Re: RISC goes CISC?
  5. Message-ID: <1992Nov9.193615.6513@csrd.uiuc.edu>
  6. Sender: news@csrd.uiuc.edu
  7. Reply-To: j-grout@uiuc.edu
  8. Organization: UIUC Center for Supercomputing Research and Development
  9. References: <1992Nov6.092012.19239@rhein-main.de> <1992Nov8.193946.2210@cs.mcgill.ca>
  10. Date: Mon, 9 Nov 92 19:36:15 GMT
  11. Lines: 17
  12.  
  13. storm@cs.mcgill.ca (Marc WANDSCHNEIDER) writes:
  14.  
  15. >    Given current technologies, it could end up being EXTREMELY difficult
  16. >to make instructions  execute in one clock cycle, if the clock cycles starting
  17. >dropping below a certain time.  There is just so much that goes on, and gates
  18. >can only go so fast.  Thus, the compromize is to try and overlap execution.
  19.  
  20. Note that this can be done either through superscalar (multiple
  21. execution units/pipelines) or superpipelining (very short cycle time
  22. with multiple pipeline stages for things like decode and execute)
  23. techniques or both (e.g., the DEC 21064 has a very fast cycle time and
  24. two parallel execution pipelines for integer and floating-point
  25. operations).
  26. --
  27. John R. Grout                        j-grout@uiuc.edu
  28. University of Illinois, Urbana-Champaign
  29. Center for Supercomputing Research and Development
  30.