NetNews Usenet Archive 1992 #26/NN_1992_26.iso/spool/comp/arch/10550

Internet Message Format | 1992-11-09 | 2.4 KB

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From: [e-mail] (Dennis O'Connor)
Newsgroups: comp.arch
Subject: Re: RTX and SC32
Date: 9 Nov 92 09:10:08
Organization: Intel i960(tm) Architecture
Lines: 36
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In-reply-to: [e-mail]'s message of Sat, 7 Nov 1992 00:29:12 GMT


[e-mail] (Adams) writes:
]  One should remember, i960 was out of discussion because of price, at
]  least here in Germany at evaluation time (about 1990). 800 US $ /chip
]  were too much, cost for development systems not included.....

Intel i960(R) microprocessors run the price gamut, from under US$20
for low-end commercial chips to a lot more for full-blown mil-spec
chips. The CA I mentioned I think sells for well under $100.

] >   And remember, it takes 4 16x16 multiplies and 3 32-bit adds
] >   ( minimum ) to do a 32x32 bit multiply. How long does that
] >   take on the FRP1600 ?
]
]  They had well known requirements, multiplying 12-14 bit operands with
]  12-14 bit coeffizients. 32 bit multiplications were not necessary.
]  Summing up 3 products, 16 bit were sufficient.

Sounds like a DSP application. At best it sounds like a 16-bit app,
not a 32-bit one. There aren't many if any 16-bit RISC processors,
and comparing architectures with different word sizes is fraught
with dangers. After all, narrower structures are inherently faster,
tho not by as much as they used to be back in the 1-level-metal days.

] >   Some older RISC architectures didn't implement fast multiply
] >   at first but added it in later products. There's no causal
] >   relationship between architectural class ( RISC, CISC, Stack, VLIW )
] >   and multiply speed.
]
]  No, but silicon already gone for cache is not available for
]  multipliers ;-<.

Every year, as yeild figures rise and device geometries shrink,
there's more silicon available for a given price point.
--
Dennis O'Connor            [e-mail]