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- Xref: sparky comp.arch:10485 comp.lang.forth:3453
- Path: sparky!uunet!auspex-gw!guy
- From: guy@Auspex.COM (Guy Harris)
- Newsgroups: comp.arch,comp.lang.forth
- Subject: Re: What's wrong with stack machines?
- Keywords: register allocation, stack cache
- Message-ID: <15381@auspex-gw.auspex.com>
- Date: 6 Nov 92 22:46:20 GMT
- References: <1992Nov6.094639.28441@email.tuwien.ac.at> <1992Nov6.182326.12025@ringer.cs.utsa.edu>
- Sender: news@auspex-gw.auspex.com
- Followup-To: comp.arch
- Organization: Auspex Systems, Santa Clara
- Lines: 49
- Nntp-Posting-Host: auspex.auspex.com
-
- >There is a perspective on RISC/register based architectures and CISC
- >and/or stack based machines.
-
- Err, does that mean you're throwing CISC machines into the same pile as
- stack-based machines? Most of the CISC architectures I've dealt with
- are register based, even though they have memory-to-register or
- memory-to-memory arithmetic; i.e....
-
- >It is: when and how do you do register
- >allocation. On a RISC machine the compiler does it.
-
- ...on those CISC machines, the compiler does it as well.
-
- >On a stack machine
- >the hardware does it on-the-fly, i.e., a particular data value or variable
- >gets allocated to a specific hardware register during execution.
-
- Hmm. I no longer have the paper, but I seem to remember seeing a paper
- on compilers for stack-based machines that, as I remember it,
- essentially had the notion of Sethi-Ullman numbers for stack machines; I
- think the goal was to reduce the maximum stack depth required to
- evaluate an expression.
-
- I.e., I'm not convinced that all the work of "register allocation" is
- always done, or should always be done, in hardware *even on stack
- machines*.
-
- (Trivial example: you can evaluate a+b+c+d as
-
- push a
- push b
- push c
- push d
- +
- +
- +
-
- or you can evaluate it as
-
- push a
- push b
- +
- push c
- +
- push d
- +
-
- If the machine has only two top-of-stack registers, the second example
- may be better than the first.)
-