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- From: cprice@mips.com (Charlie Price)
- Newsgroups: comp.arch
- Subject: Re: MIPS R4400
- Date: 6 Nov 1992 19:52:57 GMT
- Organization: MIPS Technologies, Inc
- Lines: 80
- Message-ID: <lflj8pINN158@spim.mti.sgi.com>
- References: <JCALLEN.92Nov6135200@marley.think.com>
- NNTP-Posting-Host: lloyd.mti.sgi.com
-
-
- In article <JCALLEN.92Nov6135200@marley.think.com> jcallen@marley.think.com (Jerry Callen) writes:
- >
- >The Nov 2 issue of EE Times contains an article on the new MIPS R4400
- >- 2.3 million transistors (vs 1.1 million(?) for the R4000)
- >- .6 vs .8 micron process
- >- 75MHz external clock, 150MHz internal
- >- 3.3V and 5V versions available
- >- I and D caches doubled to 16K each, still direct mapped.
-
- >The article mentions that a "large write buffer" was added.
-
- The R4400 (a.k.a R4000-A) has a buffer for uncached stores.
- The R4000 pipe stalls on uncached stores but the
- R4400 will buffer one store up and keep the pipe running.
- This will help performance doing things like writing to frame buffers.
-
- >Also, where are all the extra transistors going? I believe I've read in
- >posts by John Mashey that the R4000 uses about 600k transistors for
- >everything except the cache, which suggests that the two 8K caches on the
- >R4000 use about 500K transistors, so I might (naively) expect the two 16K
- >caches on the R4400 to use about a million. Did the write buffer consume
- >700K transistors?!?
-
- The transistors for the cache data arrays alone, not counting spare lines,
- (if I count correctly at 9 bits/byte plus 26 and 29 bits per 16 bytes
- for I and D tags respectively using 4-transistor bit cells):
- R4000 ( 8KB each): 702,752 transistors
- R4400 (16KB each): 1,405,504 transistors
-
- The R4400 implements some things not completed on the R4000 such
- as master/checker mode to build high reliability systems, so some
- transistors got used up for that stuff.
-
- >The article also says that MIPS is predicting performance at 75MHZ,
- >based on simulations, to be:
- >
- > SPECint89 = 95
- > SPECfp89 = 126
-
- The detail on this wasn't in the press release, so here it is.
-
- R4400 SC 75 MHz SPEC-89 *simulations* using IRIX "best binaries".
- The compilation flags for the binaries are whatever SGI published
- for SPEC-89 for the Crimson or Indigo-4000. They are complicated.
-
- Peak75 is intended to be the fastest uniprocessor you could reasonably
- build using this chip in order to illustrate the performance available
- from the *CHIP*.
- These parameters are not intended to represent a
- system that any vendor is currently building or will build.
-
- benchmark Peak75
- 001.gcc1.35 74.4
- 008.espresso 88.4
- 013.spice2g6 73.0
- 015.doduc 82.2
- 020.nasa7 145.
- 022.li 105.
- 023.eqntott 123.
- 030.matrix300 391.
- 042.fpppp 97.5
- 047.tomcatv 123.
-
- SPEC89mark 113.
- SPEC89int 95.3
- SPEC89fp 126.
-
- Peak75 parameters:
- clock: 75 MHz input (150 MHz processor)
- caches: primary I 16KB 8wd (32-byte) block, D 16KB 8wd block,
- joint Secondary 4MB 32wd block
- 4-pcycle initial access, 3 pcycles to second 128 bits.
- SysAddrData bus: 75 MHz, data pattern DD (Data each cycle during a block)
- memory: latency ~145ns
-
-
- --
- Charlie Price cprice@mti.sgi.com (415) 390-4457
- MS 10U-178 / MIPS Technologies / P.O. Box 7311 / Mountain View, CA 94043
-