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- Newsgroups: can.vlsi
- Path: sparky!uunet!caen!zaphod.mps.ohio-state.edu!rpi!alanzif
- From: alanzif@colossus.cs.rpi.edu (Fawaz Al-Anzi)
- Subject: Single Layer wire routing
- Message-ID: <3_3zl-l@rpi.edu>
- Summary: vlsi map
- Keywords: single layer, vlsi, map, planar graph.
- Sender: alanzif@turing.cs.rpi.edu
- Nntp-Posting-Host: colossus.cs.rpi.edu
- Organization: Rensselaer Polytechnic Institute, Troy, NY
- Date: Thu, 15 Oct 1992 17:43:24 GMT
- Lines: 38
-
- Hi everybody,
- I am doing my reseach in vlsi compaction. I have been looking
- for a real life vlsi routed single layer map. It should be a palaner
- graph, or can be considered as one. I'll be lucky if it is a bitmap
- image of the routed circuit which obay the design rules of some "lambda"
- given.
- so basically I looking for something that looks like this
-
- .--, ,--.
- ,--| |------. ,-----| | ,---.
- | `--' | | `--' | |
- | ,--|-|-----. | |
- | | | | |
- `---------| |------| |
- | | | |
- `----|-----' `-|-'
- | |
- `--------------'
-
- ftp sites will be greate ..
-
- Thank you for you help
- -Fawaz Al-Anzi
- alanzif@turing.cs.rpi.edu
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