NetNews Usenet Archive 1992 #20/NN_1992_20.iso/spool/comp/sys/intel/1649

Text File | 1992-09-08 | 2.0 KB | 46 lines

Newsgroups: comp.sys.intel
Path: sparky!uunet!spool.mu.edu!sdd.hp.com!hp-col!friedman
From: [e-mail] (John Friedman)
Subject: Re: Future of i860 line
Sender: [e-mail] (Usenet News)
Message-ID: <[e-mail]>
Date: Mon, 7 Sep 1992 15:31:18 GMT
References: <[e-mail]>
Organization: HP Colorado Springs Division
Lines: 34

[e-mail] (Kirk Hays) writes:
> [e-mail] (John Friedman) writes:
>>> [e-mail] (Mark Neidengard) writes:
>>>> Wait up.  You speak as if the i860 is not superscalar; it sure as heck IS!
>>>>
>>>> It has MULTIPLE pipelines, which can be used concurrently.  That's the
>>>> textbook definition of superscalar microprocessing.
>>>
>>> Actually, superscalar means that the processor can START executing
>>> instructions concurrently, in the same clock cycle, that is.  The 860's
>>> cannot do this, but they can be processing multiple instructions at the same
>>> time that started at different times.
>
> In that case, the i860 does meet the definition of superscalar, as an integer
> core instruction and a FPU instruction can be started in the same cycle using
> DIM (Dual Instruction Mode).  Also, a single FPU instruction can use both the
> multiply and add pipelines.  Thus, in the limit, it is possible to have both
> floating point pipelines and the integer core all working due to instructions
> that were started in the same cycle.
>
> I agree the i860 is not superscalar, so your definition must be flawed.  I
> suspect a better definition might include some words about the processor
> selecting which instructions to execute simultaneously.  The i860 doesn't do
> that, but some members of the i960 family do.

You are quite right.  In order to be truely superscalar, the processor must
be able to it own instruction scheduling, like the 960CA/CF processors do.
The 860's, as you mentioned, do not provide this function.

Thanks for pointing this out!

John Friedman
[e-mail]