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- Newsgroups: comp.sys.ibm.pc.hardware
- Path: sparky!uunet!cs.utexas.edu!torn!news.ccs.queensu.ca!mast.queensu.ca!dmurdoch
- From: dmurdoch@mast.queensu.ca (Duncan Murdoch)
- Subject: Re: Northgate's "Virtual Cache Architecture"
- Message-ID: <dmurdoch.133.715975593@mast.queensu.ca>
- Lines: 23
- Sender: news@knot.ccs.queensu.ca (Netnews control)
- Organization: Queen's University
- References: <dmurdoch.131.715960476@mast.queensu.ca>
- Date: Tue, 8 Sep 1992 18:06:33 GMT
-
- In article <dmurdoch.131.715960476@mast.queensu.ca> I wrote:
-
- >Northgate advertises that their ZXP systems have "Virtual Cache
- >Architecture". The salesman I talked to seemed unable to tell me what this
- >meant. Can anyone here?
-
- I've talked to another salesman. They use a Headland Technology "HTK340
- Shasta 486 Chip Set", which is supposed to group byte and word sized writes
- into 32 bit writes. Apparently it also groups reads; the benchmarks they
- sent showed that their system could run through PC Magazine's 128K NOP loop
- with no wait states.
-
- This is probably a great idea for most 16 bit software, but I'd guess it
- wouldn't be so great on software written to take advantage of 32 bit
- operands. If anyone has any experience with machines using this, I'd like
- to hear about it. My particular interest is in doing floating point math on
- one.
-
- They sent references to two PC Week articles: July 27/92 v9 n30 p28(1) and
- Mar 23/92 v9 n12 p34(1).
-
- Duncan Murdoch
- dmurdoch@mast.queensu.ca
-