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- Newsgroups: comp.sys.amiga.misc
- Path: sparky!uunet!news.uiowa.edu!ccad.uiowa.edu!rromano
- From: rromano@ccad.uiowa.edu (Richard A Romano)
- Subject: Re: Problems with the A4000
- Message-ID: <1992Sep15.133828.16917@ccad.uiowa.edu>
- Organization: CAD-Research, University of Iowa, Iowa City
- References: <1992Sep12.083819.17967@news.iastate.edu> <35103@cbmvax.commodore.com>
- Date: Tue, 15 Sep 1992 13:38:28 GMT
- Lines: 61
-
- In article <35103@cbmvax.commodore.com> daveh@cbmvax.commodore.com (Dave Haynie) writes:
- >
- {Intereresting stuff deleted}
-
- >The AA chipset is hardly "kludged" in. The form of the AA chipset is something
- >me, Greg, and the AA people (Bob Raible and Bill Thomas) discussed at length
- >back before there was an AA. It was designed to drop fairly easily into an
- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
- >A3000-class machine, much like ECS did. Actually, the A4000 design is
- ^^^^^^^^^^^^^^^^^^^^
- >considerably cleaned up over my A3000+ prototype, in that Greg's people did a
- >new gate array, Bridgette, which manages much of the system's datapaths more
- >efficiently than the 9 or so TTL buffers the A3000+ used to do the same job.
- >
- >Again, Mark, why do you always post stuff you have absolutely no knowledge
- >about? Especially things like the genesis of the A4000 and AA, a subject upon
- >which only a very few people could produce a real authoritative post.
- >
- >>Basically, the A3000 was not designed for the AA chipset.
- >
- >Correct. In point of fact, the AA chipset was designed for the A3000, as I
- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
- >explained above.
- >
- Why then is it "impossible" to make a daughter card containing the AA chipset
- for use in the A3000? Or is it just that it would be too much of a kludge
- for Commodore to touch.
-
- I would think judging from the responses here that a 3rd party company
- could make a lot of money with such a kludge.
-
- >--
- >Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests"
- > {uunet|pyramid|rutgers}!cbmvax!daveh BIX: hazy
- > "Work like a horse, drink like a fish" - Psychefunkapus
-
- Pardon my ignorance in asking since I have no imformation on the AA chip set
- and can't guess at the feasibility.
-
- I have a few questions:
- Is it a 32 bit data bus?
-
- I assume the chip command/register bus (terminology?) is now 16 bit from 8 or
- is it a completely new approach used?
-
- Is the data bus 14 MHz zero wait state ie 60 - 70 ns DRAMS? I've heard
- something about it being a 28 MHz bus, does it use a burst mode?
-
- Why can't it handle any line frequencies above 31kHz? 1280x400x8 bit
- sounds like the pixel rate could get high enough to support 800x600
- noninterlaced or is the 1280x400 interlaced with a deinterlacer at the
- output stage? Is the 640x400 interlaced with a deinterlacer?
-
- Thanks a lot.
-
- Rich
- --
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