NetNews Usenet Archive 1992 #20

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Xref: sparky comp.parallel:2136 comp.os.research:932 comp.arch:9433 comp.compilers:1558 Path: sparky!uunet!zaphod.mps.ohio-state.edu!cis.ohio-state.edu!rutgers!faatcrl!iecc!compilers-sender From: jwang@seas.smu.edu (Jainbai Wang) Newsgroups: comp.parallel,comp.os.research,comp.arch,comp.compilers Subject: CALL FOR PARTICIPATION -- 4th IEEE SPDP 1992 Keywords: conference, parallel, architecture Message-ID: <92-09-076@comp.compilers> Date: 14 Sep 92 17:38:11 GMT Sender: compilers-sender@iecc.cambridge.ma.us Reply-To: jwang@seas.smu.edu (Jainbai Wang) Organization: CSE Department, Univ. of Texas-Arlington, Arlington, TX Lines: 611 Approved: compilers@iecc.cambridge.ma.us ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + + CALL FOR PARTICIPATION -- SPDP 1992 + + + + Fourth IEEE Symposium on Parallel and Distributed Processing + + + + Sponsored by: IEEE-Computer Society + + IEEE-Dallas Section + + + + Arlington, Texas - December 1-4, 1992 + + + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ==================================================== | | | REGISTRATION FORM & ADVANCE PROGRAM | | | ==================================================== ======================================================================= REGISTRATION FORM ======================================================================= Fourth IEEE Symposium on Parallel and Distributed Processing Sponsored by: IEEE-Computer Society IEEE-Dallas Section Arlington, Texas - December 1-4, 1992 Chair of Steering Committee: H. Sudborough, UT. Dallas, USA Steering Committee: M. Amamiya, Kyushu Univ., JAPAN S. Bettayeb, LSU, USA P. Biswas, Cyrix, USA A. R. Hurson, PSU, USA O. Ibarra, UC, Santa Barbara, USA K. Kavi, UT. Arlington, USA V. Ramachandran, UT. Austin, USA S. Sahni, Univ. of Florida, USA B. Shirazi, UT. Arlington, USA I. Tollis, UT. Dallas, USA I. Watson, Univ of Manchester, UK General Chair: K. Hwang, Univ. of Southern California, USA Program Chairs: R. M. Keller, Harvey Mudd College, USA M. Atallah, Purdue Univ., USA B. Monien, Univ. Paderborn, Germany F. Chin, Univ. of Hong Kong, Hong Kong Program Committee: S. N. Bhatt, Yale Univ., USA K. H. Chen, Houston, USA S. W. Cheng, Hong Kong Univ of Sci & Technology, Hong Kong S. K. Das, Univ. of North Texas, USA F. E. Fich, MIT, USA & Univ. of Toronto, Canada E. Gelenbe, FRANCE A. Gupta, Stanford Univ., USA H. Imai, Kyushu, JAPAN K. P. Lam, The Chinese Univ. of Hong Kong, Hong Kong T. W. Lam, The Univ of Hong Kong, Hong Kong P. C. M. Lau, The Univ. of Hong Kong, Hong Kong T. LeBlanc, Univ. of Rochester, USA K. H. Lee, The Chinese Univ. of Hong Kong, Hong Kong M. Merritt, AT&T Bell Lab, USA R. Oldehoeft, Colorado State Univ., USA K. Padmanabhan, AT&T Bell Lab, USA C. G. Plaxton, UT. Austin, USA Registration: S. Pakzad, PSU, USA Publications: H. Y. Youn, UT. Arlington, USA This symposium provides a forum for the presentation and exchange of current work on a wide variety of topics in parallel and distributed processing including: Computer Architecture Programming Languages Operating Systems Neural Networks Interconnection Networks Database and Knowledge Artificial Intelligence Parallel Algorithms base Systems VLSI Systems Design Simulation and Modeling Distributed Computing Scheduling The technical program (December 2-4) features 44 long and 26 short papers and plenary keynote speeches by Prof. J. Hennessy of Stanford (Wed., Dec 2) Scalable Shared-Memory Multiprocessors and the Stanford DASH Approach, Prof. H. J. Siegel of Purdue (Thur., Dec. 3) Parallel Algorithm Mapping Techniques, and Prof. C. Leiserson of MIT (Fri., Dec. 4) The Network Architecture of the Connection Machine CM-5. Full-day Tutorials (December 1): T1: Parallelism Management: Synchronization, Scheduling, & Load Balancing Prof. B. Shirazi and Prof. K. Kavi, Univ of Texas Arlington. T2: Software Tools for Visualization of Parallel Programs & Systems Prof. T. Casavant, Univ. of Iowa. T3: Memory Systems for Multiprocessors & Scalable Architecture Prof. A. Choudhary, Syracuse Univ. Hotel Reservations: Please place your reservations directly with Sheraton CentrePark Hotel. 1500 Stadium Drive East, Arlington, TX 76011, Tel: (817)261-8200 or 1-800-442-PARK, (Fax: 817-261-2787). You must mention the Symposium (SPDP) in order to receive the special Symposium rates ($70/night - single room, $74/night - double room). Reservations should be made before November 10, 1992. After this date, reservations are subject to availability. ------------------------------------------------------------------------ PLEASE SEND REGISTRATION FORM AND PAYMENT (payable to SPDP) TO: Dr. Simin Pakzad, Symposium on Parallel and Distributed Processing, Dept. of Elec. & Comp. Engr., Penn State University, University Park, PA 16802, Tel: (814)863-1265. The symposium fee includes symposium proceedings, banquet, and social hour. Student registration does not include the symposium banquet. (Advance Registration: Before 11/20/92.) Symposium Tutorial IEEE Members: Advance US$240, On-Site US$290 Advance US$200, On-Site US$240 Non Members: Advance US$300, On-Site US$360 Advance US$250, On-Site US$300 Full-Time Students: Advance US$100, On-Site US$120 Advance US$200, On-Site US$240 Symposium: $_____ Tutorial: $_____ Specify choice of tutorial: ________ Total: $_____ IEEE Member:____ Non-Member:____ Student:____ IEEE No.:________________ Student ID:________________ ______Check or bank draft (US Banks ONLY) enclosed (payable to SPDP) ______Credit card (VISA or MasterCard ONLY) VISA___ MasterCard___ Credit Card No: ________________________ Expiration Date:______________ Signiture:______________________________________________________________ Last Name:_________________ First Name:_______________ Initial:________ Organization:____________________________________________________________ Address:_________________________________________________________________ City,State,Zip/Country:__________________________________________________ Telephone:_____________________ E-mail:_________________________________ ========================================================================= ADVANCE PROGRAM ========================================================================= Fourth IEEE Symposium on Parallel and Distributed Processing Sponsored by: IEEE-Computer Society, IEEE-Dallas Section Arlington, Texas - December 1-4, 1992 Plenary Keynote Speeches: Prof. John Hennessy, Stanford, Wed, Dec 2, 8:30 am: "Scalable Shared- Memory Multiprocessors and the Stanford DASH Approach." Prof. H. J. Siegel, Purdue, Thu, Dec 3, 7:30 pm: "Parallel Algorithm Mapping Techniques." Prof. Charles Leiserson, MIT, Fri, Dec 4, 9:00 am: "The Network Architecture of the Connection Machine CM-5." Social Programs: Social Hour, Cash Bar, Wed, Dec 2, 5:30 - 7:00 pm, Ballroom Foyer. Symposium Banquet, Thu, Dec 3, 6:30 - 9:00 pm, Hall of Fame. Tutorials: Tuesday, Dec 1, 9:00 am - 5:00 pm: T1: "Parallelism Management: Synchronization, Scheduling, and Load Balancing ," World Series I. Prof. Behrooz Shirazi and Prof. Krishna Kavi, University of Texas at Arlington This tutorial first presents an introduction to the fundamental issues in multiprocessing, i.e., synchronization and memory and network latencies. It then covers the program and system partitioning principles, including parallelism detection, task granularity, and architecture partitioning. Finally, the tutorial focuses on task scheduling and load balancing methods. Both static scheduling and dynamic load balancing schemes are discussed. The covered topics include task execution time estimation, communication cost estimation, static allocation methods, task migration overhead, memory systems as well as network of work-stations are considered. T2: "Software Tools for Visualization of Parallel/Distributed Programs and Systems," Super Bowl I. Prof. Thomas L. Casavant, University of Iowa This tutorial overviews major contributions to visualization for development of software for parallel/distributed computing. Emphasis is on improving the software development process for high-performance parallel computers via visualization techniques for program creation, debugging, verification, and maintenance. The topic is of growing importance for many parallel computer users, who are becoming more common as parallel systems appear in increasingly more application settings. Recent advances have come mostly from academics, but the influence on industrial and commercial settings for the future will be dramatic. General concepts, as well as a videotape illustration of practical tools, are presented. T3: "Memory Systems for Multiprocessors & Scalable Architectures," Super Bowl II. Prof. Alok N. Choudhary, Syracuse University This tutorial examines the issues in designing memory systems for large-scale multiprocessors, and is divided into four main parts. First, we will examine cache memories for multiprocessors including cache-coherence protocols, compiler techniques to maintain cache consistency and performance evaluation techniques for multiprocessor caches. Second, we will present distributed shared memory architectures and algorithms. We will also include specific case studies of several proposed systems. Third, we will discuss the designs of various experimental, as well as commercial, architectures of large-scale systems such as Stanford DASH, CM5, Intel Paragon, Kendall Square and others. Finally, we will examine several issues in designing high-performance I/O systems. Opening Session, Wednesday, Dec 2, 8:30-10:00 am, Champions I & II Ballroom Introductions: Hal Sudborough (UT-Dallas), Kai Hwang (USC), Robert M. Keller (Harvey Mudd College), and Mikhail Atallah (Purdue Univ.) Keynote Speech: Prof. John Hennessy, Stanford, "Scalable Shared-Memory Multiprocessors and the Stanford DASH Approach." Wednesday, Dec 2, 10:00-10:30 am, Break. Wednesday, Dec 2, 10:30-12:00 noon: Session 1A, Fault Tolerant Structures, Champions I Chair: Greg Plaxton, University of Texas at Austin l: Broadcasting Algorithms in Faulty SIMD Hypercubes C.S. Raghavendra, Washington State University, and M.A. Sridhar, University of South Carolina l: Tolerating Faults in a Mesh with a Row of Spare Nodes Jehoshua Bruck, Robert Cypher, and Ching-Tien Ho, IBM Almaden Research Center l: Fault-Tolerant Embeddings of Rings, Meshes, and Tori in Hypercubes Alexander Wang and Robert Cypher, IBM Almaden Research Center Session 1B, Scheduling, Champions II Chair: D.P. Agrawal, North Carolina State University l: SMALL: A Scalable Multithreaded Architecture to Exploit Large Locality R. Govindarajan, McGill University l: Impact of Workload Partitionability on the Performance of Coupling Architectures for Transaction Processing Philip S. Yu and Dan Asit, IBM Watson Research Center s: Virtual Threads Wolfgang Kuechlin and Jeff Ward, Ohio State University s: Event Scheduling in Window Based Parallel Simulation Schemes Rassul Ayani, Georgia Institute of Technology, and Hassan Rajael, Royal Institute of Technology Wednesday, Dec 2, 12:00-1:30 pm, Lunch Break. Wednesday, Dec 2, 1:30-3:00 pm: Session 2A, Mesh Connected Arrays, Champions I Chair: F. Dehne, Carleton University l: Revisiting the Allocation of Regular Data Arrays to a Mesh of Processors S. Miguet and Virginie Poty, Institut INMAG l: Optimal Algorithms for Selection on a Mesh-Connected Processor Array D. Krizanc, Carleton University, and Lata Narayanan, University of Manitoba l: Mapping Tree-Structured Computations onto Mesh-Connected Arrays of Processors J-J. Tsay, National Chung Cheng University Session 2B, Applications, Champions II Chair: Steve Wallach, Convex Computers l: Parallel Image Sequence Coding on Multiprocessor Systems Sanjeev Rampal and Dharma Agrawal, North Carolina State Univ. l: A General Purpose Distributed Implementation of Simulated Annealing R. Diekmann, R. Luling, and J. Simon, University of Paderborn s: Surface Reconstruction in Parallel Sunjay Talede, Theodore Johnson, and Panos E. Livadas, University of Florida s: An Exact Hardware Implementation of the Boltzmann Machine Marcin Skubiszewski, Digital Equipment Corporation Wednesday, Dec 2, 3:00-3:30 pm, Break. Wednesday, Dec 2, 3:30-5:00 pm: Session 3A, Scheduling, Champions I Chair: J. Abello, Texas A&M l: Optimal and Near Optimal Tree Scheduling for Parallel Systems C.L. McCreary, Auburn University, and Y. Zhu, North Dakota University l: An NC Algorithm for Finding Minimum Weighted Completion Time Schedule on Series Parallel Graphs S. Sunder and Xin He, SUNY Buffalo l: On Uniformization of Affine Dependence Algorithms Zhigang Chen and Weijia Shang, University of Southwestern Louisiana Session 3B, Fault Tolerant Architectures, Champions II Chair: Dhiraj Pradhan, Texas A&M University l: Evaluating Reliability Improvements of Fault Tolerant VLSI Processor Arrays D. L. Tao, SUNY at Stony Brook l: Pipelined Circuit-Switching: A Fault-Tolerant Variant of Wormhole Routing Patrick T. Gaughan and Sudhakar Yalamanchili, Georgia Institute of Technology s: Fault Tolerance of Adaptive Routing Algorithms in Multicomputers A.L. Narasimha Reddy and Rich Freitas, IBM Almaden Research Center s: Hierarchical Interconnection Networks: Routing in the Presence of Faults Besomsu Kim and Hee Y. Youn, University of Texas at Arlington Wednesday, Dec 2, 5:30-7:00 pm, Social Hour, Cash bar, Ballroom Foyer. Thursday, Dec 3, 8:30-10:00 am: Session 4A, Algorithms, Champions I Chair: D. Matula, Southern Methodist University l: A New Framework for Designing Parallel Algorithms on Series Parallel Graphs Yuval Caspi and Eliezer Dekel, University of Texas at Dallas l: A Divide and Conquer Approach to Shortest Paths in Planar Layered Digraphs S. Sairam, Roberto Tamassia, and Jeffrey Scott Vitter, Brown University s: A Fast Parallel Algorithm for the Single Link Heuristics of Hierarchical Clustering Elias Dahlhaus, University of Sydney s: The p-Shovelers Problem (Computing with Time-Varying Data) F. Luccio and L. Pagli, Universita di Pisa Session 4B, Compilation, Champions II Chair: Vijay Raj, University of Texas at Arlington l: Termination Detection for Synchronous Parallel Iterative Computations C.Z. Xu and Francis C.M. Lau, The University of Hong Kong s: Extended Cycle Shrinking: An Optimal Loop Transformation Chun Gong, University of Pittsburgh s: Advanced Software Pipelining and the Program Dependence Graph R.M. Lee and V.H. Allan, Utah State University Thursday, Dec 3, 10:00-10:30 am, Break. Thursday, Dec 3, 10:30-12:00 noon: Session 5A, Networks, Champions I Chair: I. Parberry, University of North Texas l: An Algebraic Framework for Edge-Disjoint Permutations on Hypercubes Arch D. Robison and Danny Soroker, Shell Development Company l: Distributed Computing on Cayley Networks Evangelos Kranakis and Danny Krizanc, Carleton University s: Optimal Embeddings of Ternary Trees into Boolean Hypercubes Ajay K. Gupta and Hong Wang, Western Michigan University Session 5B, Communication Issues, Champions II Chair: Sudhakar Yalamanchili, Georgia Institute of Technology l: Using Communication-to-Computation Ratio in Parallel Program Design and Performance Prediction Mark Crovella, Ricardo Bianchini, Thomas LeBlanc, Evangelos Markatos and Robert Wisniewski, University of Rochester l: Hierarchy of Communication Speeds: Definition, Uses in Designing Concurrent Systems and Implementation. Mohan Ahuja, University of California, San Diego and Ravi Prakash, Ohio State University l: Shared Memory vs. Message Passing in Shared-Memory Multiprocessors Thomas J. LeBlanc and Evangelos Markatos, University of Rochester Thursday, Dec 3, 12:00-1:30 pm, Lunch Break. Thursday, Dec 3, 1:30-3:00 pm: Session 6A, Distributed Systems, Champions I Chair: M. Gouda, University of Texas at Austin l: Two System Calculation Algorithms for Optimal Load Balancing Andreas Winckler, Universitaet Stuttgart l: An (N-1)-Resilient Algorithm for Distributed Termination Detection Ten-Hwang Lai and Li-Fen Wu, Ohio State University s: Multiple Tree Quorum Algorithm for Replica Control in Distributed Database Systems Soon M. Chung and Cailin Cao, Wright State University Session 6B, Problem Solving, Champions II Chair: Doug Degroot, Texas Instruments l: Complete and Efficient Methods for Supporting Side-Effects and Cuts in And-Or Parallel Prolog Gopal Gupta, New Mexico State University and Vitor Santos Costa, University of Bristol l: The Dharma Scheduler - Definitive Scheduling in Aurora on Multiprocessor Architectures R. Sindaha, University of Bristol s: A High-Level, Object-Oriented Approach to Divide-and-Conquer A.J. Piper and R.W. Prager, Cambridge University Thursday, Dec 3, 3:00-3:30 pm, Break. Thursday, Dec 3, 3:30-5:00 pm: Session 7A, Models and Algorithms, Champions I Chair: Russ Miller, SUNY Buffalo l: The Parallel Asynchronous Recursion Model Lisa Higham and Eric Schenk, University of Calgary l: The Complexity of Sequential Consistency Ephraim Korach and Phil Gibbons, ATT Laboratories l: A Fast Sort Using Parallelism Within Memory Claudia Leopold, Humboldt Universitaet Berlin Session 7B, Processor Allocation, Champions II Chair: Thomas LeBlanc, University of Rochester l: A Novel Approach for Subcube Allocation in Hypercube Multiprocessors Dehendra Das Sharma and Dhiraj K. Pradhan Texas A&M University l: A Balanced Layer Allocation Scheme for Hypercube Based Dataflow Systems V.R. Freytag, B. Lee, Oregon State University, and A.R. Hurson, Pennsylvania State University s: Time Sharing in Hypercube Multiprocessors Eliseu M. Chaves Filho, COPPE/UFRJ, and Valmir C. Barbosa, IBM Rio Scientific Center s: On the Distributed Subcube-Allocation and Job-Scheduling Strategies in Hypercube Multiprocessor Systems Jyh-Charn Liu and Yilong Chen, Texas A&M University Thursday, Dec 3, 6:30-9:00 pm, Symposium Banquet, Hall of Fame. Keynote Speech: Prof. H. J. Siegel, Purdue, Thu, Dec 3, 7:30 pm: "Parallel Algorithm Mapping Techniques." Friday, Dec 4, 9:00-10:00 am, Champions I & II Ballroom: Keynote Speech: Prof. Charles Leiserson, MIT, Fri, Dec 4, 9:00 am: "The Network Architecture of the Connection Machine CM-5." Friday, Dec 4, 10:00-10:30 am, Break. Friday, Dec 4, 10:30-12:00 noon: Session 8A, Networks & Algorithms, Champions I Chair: S. Das, University of North Texas l: Bounds on the Diameter of PEC Networks Cho-Chin Lin and Viktor K. Prasanna, University of Southern California l: Deterministic Routing on Circular Arrays J.F. Sibeyn, Utrecht University l: An Optimal Multiplication Algorithm on Reconfigurable Mesh Ju-wook Jang, Heonchul Park, and Viktor K. Prasanna, University of Southern California Session 8B, Distributed Systems, Champions II Chair: Paraskevas Evripidou, Southern Methodist University l: Page Replacement in Distributed Virtual Memory Systems Mohammad I. Malkawi, Deborah L. Knox, and Mahmoud Abaza, University of Wisconsin, Milwaukee s: Debugging Dynamic Distributed Programs using Global Predicates Yoshifumi Manabe and Shigemi Aoyagi, NTT Software Laboratories s: A Token Based Distributed K Mutual Exclusion Kia Makki, Paul Banta, Ken Been, University of Nevada, Las Vegas, and Niki Pissinou, University of Southern California s: Modeling Resource Contention for Distributed Periodic Processes Lonnie R. Welch, Alexander D. Stoyenko, New Jersey Institute of Technology, and Thomas J. Marlowe, Seton Hall University s: An Implementation of Flush Channels for Possibly Cyclic Networks Xuefeng Dong, Ohio State University, and Mohan Ahuja, University of California, San Diego Friday, Dec 4, 12:00-1:30 pm, Lunch Break. Friday, Dec 4, 1:30-3:00 pm: Session 9A, Miscellaneous, Champions I Chair: K. Efe, University of Southwestern Louisiana l: Multiple Message Broadcasting With Generalized Fibonacci Trees Jehoshua Bruck, Robert Cypher, and Ching-Tien Ho, IBM Almaden Research Center l: A Key to Parallelism in Public Key Cryptography C. Posch and R. Posch, Technische Universitaet Graz s: A Methodology for Generating Data Distributions to Optimize Communication S.K.S. Gupta, S.D. Kaushik, C.-H. Huang, Ohio State University, J.R. Johnson, Drexel University, R.W. Johnson, St. Cloud State University, and P. Sadayappan, Ohio State University Session 9B, Architecture, Champions II Chair: Paul Chiang, Texas Instruments l: Memory Architecture Support for the SIMD Construction of a Gaussian Pyramid Jong Won Park, Chung-Nam National University, and D.T. Harper III, University of Texas at Dallas l: Programming Environment for Phase-Reconfigurable Parallel Programming on SuperNode J.M. Adamo, C. Bonello, and L. Trejo, Ecole Normale Superieure de Lyon l: Single Processor-Pool MSIMD/MIMD Architectures M.S. Baig, T.A. El-Ghazawi, and N.A. Alexandridis, George Washington University Friday, Dec 4, 3:00-3:30 pm, Break. Friday, Dec 4, 3:30-5:00 pm: Session 10A, Interconnection Networks, Champions I Chair: S. Pakzad, Pennsylvania State University l: An Evaluation of Planar-Adaptive Routing (PAR) Jae H. Kim and Andrew Chien, University of Illinois at Urbana-Champaign s: Hyperweave: A Fault-Tolerant Expandable Interconnection Network Gowri Ramanathan, Mark Clement, and Phyllis Crandall, Oregon State University s: A New Class of Interconnection Networks Based on the Alternating Group Jung-Sing Jwo, S. Lakshmivarahan, and S.K. Dhall, University of Oklahoma s: Efficient Networks for Realizing Permutation and Unicast Assignments in Parallel Processors Ming Lu and A. Yavuz Oruc, University of Maryland s: Hierarchical Shuffle-Exchange and de Bruijn Networks Robert Cypher and Jorge L.C. Sanz, IBM Almaden Research Center Session 10B, Cache-Coherent Architectures, Champions II Chair: Hee Y. Youn, University of Texas at Arlington l: Scalable Tree Protocol - A Cache Coherence Approach for Large-Scale Multiprocessors Hakan Nilsson and Per Stenstrom, Lund University l: Efficient Evaluation of Arbitrary Set-Associative Caches on Multiprocessors Yuguang Wu, University of California, Los Angeles s: Cache Coherent Shared Memory Hypercube Multiprocessors Jianxun Ding and Laxmi Bhuyan, Texas A&M University s: Software Caching on Cache-Coherent Multiprocessors Ricardo Bianchini and Thomas J. LeBlanc, University of Rochester ___________________________________________________________________________ l: 30-min presentation, s: 15-min presentation -- Send compilers articles to compilers@iecc.cambridge.ma.us or {ima | spdcc | world}!iecc!compilers. Meta-mail to compilers-request.