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- Newsgroups: comp.arch
- Path: sparky!uunet!spool.mu.edu!darwin.sura.net!ua1ix!carlrs6000.carl.ua.edu!jjackson
- From: jjackson@carlrs6000.carl.ua.edu (Jeff Jackson)
- Subject: Adder Designs in Modern Microprocessors
- Message-ID: <1992Sep10.150553.141904@ua1ix.ua.edu>
- Sender: news@ua1ix.ua.edu
- Nntp-Posting-Host: carlrs6000.carl.ua.edu
- Organization: The University of Alabama
- Date: Thu, 10 Sep 1992 15:05:53 GMT
- Lines: 34
-
- i
- And now back to computer architecture related material.....
-
- Out of curiosity and for general distribution to my computer engineering
- class, I am trying to compile information on various integer unit adder
- designs used in current micros (i.e. any RISC, 486, 68XXX, etc.)
-
- I am especially interested in the following points:
-
- 1. Adder configuration: ripple carry, RC (doubtful); carry lookahead, CLA
- RC-CLA hybrids, carry skip (single or multistage),
- carry select, others?
-
- 2. Propagation delay time through the adder. (gate and line delays)
-
- 3. Implementation Technology
-
- 4. Die area utilized: square mils or % of total area. The latter is probably
- more interesting to me.
-
- 5. Presence of multiple ALUs.
-
- 6. Evolution of adder design from earlier micros.
-
- Is there a common source for this information? Thanks in advance.
-
- -------------------------------------------------------------------------------
- David Jeff Jackson Internet: jjackson@tiger.carl.ua.edu
- Electrical Engineering Dept. (130.160.48.25)
- P.O. Box 870286
- The University of Alabama The Computer Architecture Research Lab
- Tuscaloosa, AL 35487-0286
- Phone: (205) 348-2919
- -------------------------------------------------------------------------------
-