NetNews Usenet Archive 1992 #20/NN_1992_20.iso/spool/comp/arch/9293

Text File | 1992-09-08 | 1.3 KB | 33 lines

Newsgroups: comp.arch
Path: sparky!uunet!sun-barr!ames!agate!dog.ee.lbl.gov!hellgate.utah.edu!fcom.cc.utah.edu!phil
From: [e-mail] (Phillip Neiswanger)
Subject: No Branch Delay Slot(s)...
Message-ID: <[e-mail]>
Sender: [e-mail]
Organization: University of Utah Computer Center
Date: Wed, 9 Sep 92 04:42:31 GMT
Lines: 22

Hi,

Before I state my question I would like to appologize to all who have been
bothered by my rather inane posts in the past.  They will remain just that;
posts of the past.

In the august issue of Byte there is a rather lightweight article on DEC's
Alpha architecture and its current incarnate the 21064.  In the article it
states that DEC deemed the branch delay slot to be of little value in
future multiple(read >2) instruction issue implementations of the Alpha
architecture.  If I remember correctly, the article states that the use of
delayed branch slots could introduce incompatibilities from implementation
to implementation.  This does not seem very intuitive to me.  Would anybody
care to discuss how branch delay slots are going to affect future generation
of RISC cpus as they enter the era of multiple(read >2) instruction issue
implementations.

There.  I hope that was a much more interesting question. :)

                Phil
                email:    [e-mail]
                    [e-mail]