home *** CD-ROM | disk | FTP | other *** search
- Newsgroups: comp.lsi.cad
- Path: sparky!uunet!cis.ohio-state.edu!news.sei.cmu.edu!fs7.ece.cmu.edu!hagerman
- From: hagerman@ece.cmu.edu (John Hagerman)
- Subject: Re: How to measure regularity in CDFGs ? Help !!
- In-Reply-To: aranake@cse.uta.edu's message of 25 Aug 92 17:33:51 GMT
- Message-ID: <HAGERMAN.92Aug26120839@rx7.ece.cmu.edu>
- Sender: news@fs7.ece.cmu.edu (USENET News System)
- Organization: Carnegie Mellon University
- References: <1992Aug25.173351.7393@cse.uta.edu>
- Distribution: usa
- Date: Wed, 26 Aug 1992 17:08:39 GMT
- Lines: 23
-
- In article <1992Aug25.173351.7393@cse.uta.edu> aranake@cse.uta.edu (Sandeep Suresh Aranake) writes:
-
- Can someone suggest a metric to represent the regularity
- in digital systems described using CDFGs?
-
- A few references from a quick look through the '92 DAC proceedings:
-
-
- "Time Constrained Allocation and Assignment Techniques for High
- Throughput Signal Processing", W. Geurts, F. Catthoor, H. De Man.
-
- "Partitioning by Regularity Extraction", D. Rao, F. Kurdahi.
-
- "Functional Synthesis Using Area and Delay Optimization", E.
- Rundensteiner, D. Gajski.
-
-
- These may not answer your question (if I understand it correctly), but
- they may at least point toward an answer.
-
- - John
- --
- hagerman@ece.cmu.edu
-