home *** CD-ROM | disk | FTP | other *** search
/ NetNews Usenet Archive 1992 #19 / NN_1992_19.iso / spool / comp / lsi / 574 < prev    next >
Encoding:
Internet Message Format  |  1992-09-02  |  1.4 KB
  1. Xref: sparky comp.lsi:574 comp.lsi.cad:926
  2. Path: sparky!uunet!pmafire!news.dell.com!swrinde!zaphod.mps.ohio-state.edu!usc!wupost!darwin.sura.net!jvnc.net!yale.edu!ira.uka.de!math.fu-berlin.de!zrz.tu-berlin.de!cs.tu-berlin.de!ronald
  3. From: ronald@opal.cs.tu-berlin.de (Ronald Hindmarsh)
  4. Newsgroups: comp.lsi,comp.lsi.cad
  5. Subject: Netlists with complex gates from high level circuit description?
  6. Keywords: cmos complex gates vlsi netlists
  7. Message-ID: <1992Sep2.173615.23186@cs.tu-berlin.de>
  8. Date: 2 Sep 92 17:36:15 GMT
  9. Sender: news@cs.tu-berlin.de
  10. Organization: Techn. University of Berlin, Germany
  11. Lines: 25
  12.  
  13.  
  14. Hello net-working users!
  15.  
  16. I am working on a VLSI module generator, which includes automatic
  17. layout design of static CMOS complex gates. I would like to
  18. know, whether there exists a software solution to break some
  19. high level circuit description into a gate level description, which
  20.  
  21. a) uses complex gates of a given library,
  22.  
  23. or
  24.  
  25. b) 'invents' those complex gates, which leads to a minimal gate count
  26.    of the circuit.
  27.  
  28. Any experience or pointers?
  29.  
  30.  
  31. ----------------------------------------------------------------------
  32.  Ronald Hindmarsh                      e-mail: ronald@cs.tu-berlin.de
  33.  Institut fuer Technische Informatik
  34.  TU Berlin FR 3-9
  35.  Franklinstr. 29                            Phone: (+49) 30 314-73432
  36.  W-1000 Berlin 10                             Fax: (+49) 30 314-21103
  37. ----------------------------------------------------------------------
  38.