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- Newsgroups: comp.lang.vhdl
- Path: sparky!uunet!wupost!eclnews!cec2!jab3
- From: jab3@cec2.wustl.edu (John Alonzo Breen)
- Subject: Re: VHDL Problem - Procedures & Processes
- Message-ID: <1992Aug27.125636.3191@wuecl.wustl.edu>
- Sender: usenet@wuecl.wustl.edu (Usenet Administrator)
- Nntp-Posting-Host: cec2
- Organization: Washington University, St. Louis Mo.
- References: <1992Aug25.172750.11830@babbage.ece.uc.edu>
- Distribution: usa
- Date: Thu, 27 Aug 1992 12:56:36 GMT
- Lines: 19
-
- In article <1992Aug25.172750.11830@babbage.ece.uc.edu> pmamtora@pumpkin.ece.uc.edu (Paddy Mamtora) writes:
- >1.Can you call a procedure from two different processes ? If not,
- >then, is there any way to getting around it ?
-
- I know for a fact that procedures without signal assignments can be
- called from more than one process, and I'm pretty sure that procedures
- with signal assignments can also (but see below).
-
- >2. In a procedure, can you assign to signals that are declared
- >to be ports of the entity ? ( without declaring any
- >formal parameters for the signals in the procedure declaration)
-
- As I recall, there were some problems with this; something about the
- analyzer/simulator not being able to tell which process (and
- accompanying driver) to associate with the assignment. Maybe one of
- the "language police" will elaborate.
- --
- John A. Breen |
- jab3@cec1.wustl.edu | This space unintentionally left blank
-