NetNews Usenet Archive 1992 #19/NN_1992_19.iso/spool/comp/lang/vhdl/422

Internet Message Format | 1992-08-25 | 1.0 KB

Path: sparky!uunet!seismo!darwin.sura.net!zaphod.mps.ohio-state.edu!pacific.mps.ohio-state.edu!linac!att!news.cs.indiana.edu!uceng.uc.edu!babbage.ece.uc.edu!pumpkin.ece.uc.edu!pmamtora
From: [e-mail] (Paddy Mamtora)
Newsgroups: comp.lang.vhdl
Subject: VHDL Problem - Procedures & Processes
Message-ID: <[e-mail]>
Date: 25 Aug 92 17:27:50 GMT
Sender: [e-mail] (Operator)
Distribution: usa
Organization: Unversity of Cincinnati, ECE Dept
Lines: 21
Nntp-Posting-Host: pumpkin.ece.uc.edu

Hi,

I had two queries regarding usage of procedures in VHDL.

1.Can you call a procedure from two different processes ? If not,
then, is there any way to getting around it ?

2. In a procedure, can you assign to signals that are declared
to be ports of the entity ? ( without declaring any
formal parameters for the signals in the procedure declaration)


Thanks,


--
Padmanabh Mamtora 'Paddy'
Email : [e-mail]
Phone : [phone] (H)
    [phone] (O)
Fax   : [phone]