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Text File  |  1992-09-02  |  563 b   |  16 lines
  1. Newsgroups: comp.lang.verilog
  2. Path: sparky!uunet!munnari.oz.au!hp9000.csc.cuhk.hk!uxmail!uxmail.ust.hk!eekhfung
  3. From: eekhfung@uxmail.ust.hk (Fung Ka Hing)
  4. Subject: Analogue modeling by Verilog
  5. Message-ID: <1992Sep3.071552.9412@uxmail.ust.hk>
  6. Summary: Enquiry for information
  7. Sender: eekhfung@hkust.hk
  8. Organization: Hong Kong University of Science and Technology
  9. Date: Thu, 3 Sep 1992 07:15:52 GMT
  10. Lines: 4
  11.  
  12. I am a new learner of verilog.  I want to find some information about the
  13. ability of modelling analog circuit by verilog.  
  14.  
  15. Would someone help me please?
  16.