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- Path: sparky!uunet!ogicse!das-news.harvard.edu!spdcc!iecc!compilers-sender
- From: sanjay@equalizer.cray.com (+Sanjay Krishnamurthy)
- Newsgroups: comp.compilers
- Subject: Loop scheduling/Register Allocation refs.
- Keywords: registers, optimize, bibliography
- Message-ID: <92-08-177@comp.compilers>
- Date: 29 Aug 92 20:26:16 GMT
- Article-I.D.: comp.92-08-177
- References: <92-08-154@comp.compilers>
- Sender: compilers-sender@iecc.cambridge.ma.us
- Reply-To: sanjay@equalizer.cray.com (+Sanjay Krishnamurthy)
- Organization: Compilers Central
- Lines: 36
- Approved: compilers@iecc.cambridge.ma.us
-
- >[Is there} any published paper about the interaction between
- >loop scheduling and register allocation and the algorithms for combining
- >these two parts?
-
- You might want to look at:
-
- "Register Allocation for Modulo Scheduled Loops: Strategies,
- Algorithms and Heuristics," in the proc. of the ACM SIGPLAN
- 1992 Conf. on Prog. Lang. Design and Implementation,
- San Fransisco, June 1992.
- A more detailed version appears as a HP Tech. Report(HPL-92-48).
-
- "Compiler Techniques for Optimizing Memory and Register
- Usage on the Cray-2," C. Eisenbeis, W. Jalby and A. Lichnewsky,
- Intl. Journal of High Speed Computing,
- Vol. 2, No. 2 (1990), pp. 193-222.
- A conference version of the same paper appears as:
- "Squeezing more CPU Performance out of a Cray-2 by Vector
- Block Scheduling," Supercomputing 1988, Florida.
-
- The goals of vector register allocation and allocation
- during loop scheduling are identical. Hence, try:
-
- "Vector Register Allocation," Randy Allen and Ken Kennedy,
- Rice University Computer Science Dept. Tech. Report,
- COMP TR86-45.
-
- Somebody more familiar with register allocation than I am
- might want to add references to this list.
-
- Ciao...
- -Sanjay M. Krishnamurthy
- Cray Research Superservers
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