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- Newsgroups: comp.arch
- Path: sparky!uunet!haven.umd.edu!darwin.sura.net!wupost!rice!helena.cs.rice.edu!preston
- From: preston@helena.cs.rice.edu (Preston Briggs)
- Subject: Re: Multi threaded CPUs
- Message-ID: <BtxJDM.CK@rice.edu>
- Sender: news@rice.edu (News)
- Organization: Rice University, Houston
- References: <1811llINN3ci@usenet.INS.CWRU.Edu> <BtxGvn.8MH@pix.com> <BtxHG0.8rz@pix.com>
- Date: Wed, 2 Sep 1992 02:39:22 GMT
- Lines: 28
-
- stripes@pix.com (Josh Osborne) writes:
-
- >A little while ago I read about a RISC CPU (SPARC I think) that some
- >researchers had designed. It had a cache of threads (I got the impresion
- >that that includes registers, and posabble MMU state as well), four in
- >the current chip, and when there was a pipe stall the execution would just
- >switch to another thread.
-
- Anant Agarwal, at MIT, was working on a modification of the SPARC,
- called Sparcle, to be used as a node in a large-scale multiprocessor
- called Alewife. He gave a talk on the project last year at a workshop
- during Supercomputing '91. Unfortunately, I have only a brief
- abstract here.
-
- My memory from the talk was that they used each set of registers in
- the SPARC's register windows to support a different thread. Can
- switch threads in 11 cycles. Probably use the multithreaded behaviour
- to hide communication latency.
-
- There have been other multithreaded machines in the past, and new ones
- are still being built. In some cases, they switch to enable a greater
- degree of pipelining (ala the Denelcor HEP). Modern machines seem to
- use multithreading to hide the latency of memory access (ala the Tera
- machine) or communication.
-
- Authors to look for include Agarwal, Arvind, and Burton Smith.
-
- Preston Briggs
-